Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
195 lines
8.9 KiB
C
195 lines
8.9 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "aes-engine.h"
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void aes_engine_init(struct aes_engine *s)
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{ if (s) { aes_clear(s,sizeof(*s));s->ready=1; } }
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static uint32_t key_bytes(uint32_t header)
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{ return 16+8*((header>>22)&3); }
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static void bytes_be(uint8_t *out,const uint32_t *words,unsigned n)
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{ for (unsigned i=0;i<n;i++) out[i]=(uint8_t)(words[i/4]>>(24-8*(i&3))); }
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struct span { volatile uint8_t *p;size_t n; };
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#define SPANS (AES_TRANSFER_MAX/0x4000+1)
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static int overlap(uintptr_t a,size_t an,uintptr_t b,size_t bn)
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{ return a<b+bn && b<a+an; }
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static int maps(const struct aes_dma *m,const struct aes_engine *s,uint64_t iova,size_t n,
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int write,struct span *out,unsigned *count)
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{
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if (!m || !m->map || !m->publish || !n || iova>=(1UL<<42) || n>(1UL<<42)-iova) return 0;
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*count=0;
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while (n) {
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size_t take=0x4000-(iova&0x3fff);if (take>n) take=n;
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volatile uint8_t *p=m->map(m->ctx,iova,take,write);
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uintptr_t a=(uintptr_t)p,b=(uintptr_t)s;
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if (!p || a>UINTPTR_MAX-take || b>UINTPTR_MAX-sizeof(*s) ||
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overlap(a,take,b,sizeof(*s)) || *count>=SPANS) return 0;
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out[(*count)++]=(struct span){p,take};iova+=take;n-=take;
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}
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return 1;
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}
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static uint8_t get_byte(const struct span *s,size_t offset)
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{ while (offset>=s->n) { offset-=s->n;s++; }return s->p[offset]; }
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static void put_byte(const struct span *s,size_t offset,uint8_t value)
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{ while (offset>=s->n) { offset-=s->n;s++; }s->p[offset]=value; }
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static enum aes_result crypt(struct aes_engine *s,const struct aes_dma *m,uint32_t h,const uint32_t *w)
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{
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unsigned ks=(h>>27)&1,is=(h>>25)&3;size_t n=h&0x1ffffff;
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const struct aes_slot *key=&s->keys[ks];
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if (!n || (n&15) || n>AES_TRANSFER_MAX || !key->valid ||
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(key->key.rounds!=10 && key->key.rounds!=12 && key->key.rounds!=14) ||
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key->encrypt>1 || key->mode>2 || (key->mode && !(s->iv_valid&(1U<<is)))) return AES_BAD_STATE;
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/* J700 26A428 _pushCommandBuffer, 0xfffffe00099351c4..51f8:
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* the first low address (source) has its high bits in [25:16]. */
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if (w[0]&~0x03ff03ffU) return AES_UNSUPPORTED;
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uint64_t src=((uint64_t)((w[0]>>16)&0x3ff)<<32)|w[1];
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uint64_t dst=((uint64_t)(w[0]&0x3ff)<<32)|w[2];
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struct span in[SPANS],out[SPANS];unsigned ni,no;
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if (!maps(m,s,src,n,0,in,&ni) || !maps(m,s,dst,n,1,out,&no)) return AES_DMA_REFUSED;
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/* Exact physical in-place is supported even through different IOVAs.
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* Partial overlap or output aliases must not clobber future input. */
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size_t aoff=0;
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for (unsigned a=0;a<no;a++) {
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for (unsigned b=0;b<a;b++)
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if (overlap((uintptr_t)out[a].p,out[a].n,(uintptr_t)out[b].p,out[b].n)) return AES_DMA_REFUSED;
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size_t boff=0;
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for (unsigned b=0;b<ni;b++) {
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if (overlap((uintptr_t)out[a].p,out[a].n,(uintptr_t)in[b].p,in[b].n) &&
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(uintptr_t)out[a].p-aoff!=(uintptr_t)in[b].p-boff) return AES_DMA_REFUSED;
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boff+=in[b].n;
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}
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aoff+=out[a].n;
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}
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uint8_t iv[16],input[16],block[16];
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for (unsigned j=0;j<16;j++) iv[j]=s->iv[is][j];
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for (size_t off=0;off<n;off+=16) {
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for (unsigned j=0;j<16;j++) input[j]=get_byte(in,off+j);
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if (key->mode==2) {
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(void)aes_block(&key->key,iv,block,0);
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for (unsigned j=0;j<16;j++) block[j]^=input[j];
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for (unsigned j=16;j>0;j--) if (++iv[j-1]) break;
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} else {
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for (unsigned j=0;j<16;j++) block[j]=input[j]^((key->mode && key->encrypt) ? iv[j] : 0);
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(void)aes_block(&key->key,block,block,!key->encrypt);
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if (key->mode) for (unsigned j=0;j<16;j++) {
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if (!key->encrypt) block[j]^=iv[j];
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iv[j]=key->encrypt ? block[j] : input[j];
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}
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}
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for (unsigned j=0;j<16;j++) put_byte(out,off+j,block[j]);
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}
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for (unsigned i=0;i<no;i++) m->publish(m->ctx,out[i].p,out[i].n);
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if (key->mode) for (unsigned j=0;j<16;j++) s->iv[is][j]=iv[j];
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s->transfers++;s->bytes+=n;
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aes_clear(iv,sizeof(iv));aes_clear(input,sizeof(input));aes_clear(block,sizeof(block));
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return AES_OK;
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}
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static enum aes_result get_iv(struct aes_engine *s,const struct aes_dma *m,uint32_t h,uint32_t low)
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{
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/* The shipped version-5 driver exports slot zero, 9934e30..9934e60.
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* Other GET_IV encodings remain unsupported until established. */
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if (!(s->iv_valid&1)) return AES_BAD_STATE;
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uint64_t dst=((uint64_t)(h&0x3ff)<<32)|low;
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struct span out[SPANS];unsigned count;
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if (!maps(m,s,dst,16,1,out,&count)) return AES_DMA_REFUSED;
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for (unsigned i=1;i<count;i++)
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if (overlap((uintptr_t)out[0].p,out[0].n,(uintptr_t)out[i].p,out[i].n)) return AES_DMA_REFUSED;
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for (unsigned i=0;i<16;i++) put_byte(out,i,s->iv[0][i]);
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for (unsigned i=0;i<count;i++) m->publish(m->ctx,out[i].p,out[i].n);
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s->iv_exports++;return AES_OK;
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}
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static unsigned payload_words(uint32_t v)
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{
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switch (v>>28) {
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case 1:
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if ((v&~0x18d30000U) || ((v>>22)&3)>2 || ((v>>16)&3)>2) return 0;
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return key_bytes(v)/4;
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case 2:return (v&~0x2c000000U) ? 0 : 4;
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case 5:return (!(v&0x1ffffff) || (v&15) || (v&0x1ffffff)>AES_TRANSFER_MAX) ? 0 : 3;
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case 6:return (v&~0x600003ffU) ? 0 : 1;
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default:return 0;
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}
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}
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static enum aes_result word(struct aes_engine *s,const struct aes_dma *m,uint32_t v)
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{
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if (!s->running) return AES_BAD_STATE;
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if (!s->need) {
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unsigned op=v>>28,need=payload_words(v);
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switch (op) {
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case 1:case 2:case 6:
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if (!need) return AES_UNSUPPORTED;
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break;
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case 5:
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if (!need) return AES_BAD_VALUE;
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break;
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case 8:
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/* performAESQuantum 9934d9c..9934db4 inserts this exact
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* synchronization command before GET_IV. DMA is synchronous
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* and already published, so no work remains to drain. It must
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* not raise FLAG or replace the completion tag. */
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if (v==0x80000100U) {s->commands++;s->barriers++;return AES_OK;}
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if (v&~0x880000ffU) return AES_UNSUPPORTED;
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s->completed_tag=v&0xff;
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if (v&(1U<<27)) s->irq_status|=1U<<5;
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s->commands++;s->barriers++;return AES_OK;
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default:return AES_UNSUPPORTED;
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}
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s->header=v;s->need=need;s->used=0;return AES_OK;
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}
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if (s->used+1<s->need) { s->words[s->used++]=v;return AES_OK; }
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uint32_t words[8];for (unsigned i=0;i<s->used;i++) words[i]=s->words[i];words[s->used]=v;
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enum aes_result result=AES_OK;unsigned op=s->header>>28;
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if (op==1) {
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uint8_t bytes[32];unsigned n=key_bytes(s->header),slot=(s->header>>27)&1;
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bytes_be(bytes,words,n);(void)aes_expand(&s->keys[slot].key,bytes,n);
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s->keys[slot].valid=1;s->keys[slot].encrypt=(s->header>>20)&1;
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s->keys[slot].mode=(s->header>>16)&3;aes_clear(bytes,sizeof(bytes));
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} else if (op==2) {
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unsigned slot=(s->header>>26)&3;bytes_be(s->iv[slot],words,16);s->iv_valid|=1U<<slot;
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} else if (op==5) result=crypt(s,m,s->header,words);
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else if (op==6) result=get_iv(s,m,s->header,words[0]);
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else result=AES_BAD_STATE;
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aes_clear(words,sizeof(words));
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if (result!=AES_OK) return result;
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aes_clear(s->words,sizeof(s->words));s->header=s->need=s->used=0;s->commands++;return AES_OK;
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}
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enum aes_result aes_engine_access(struct aes_engine *s,const struct aes_dma *m,
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uint64_t off,unsigned width,int write,uint64_t *value)
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{
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if (!s || !value || s->ready!=1 || s->running>1 || s->need>8 || s->used>=8 ||
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(s->need && (s->used>=s->need || s->need!=payload_words(s->header) || !s->running)) ||
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(!s->need && (s->used || s->header)) || s->iv_valid>15 || s->completed_tag>255 ||
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(s->irq_status&~0x20U) || (s->irq_enable&~0x3efffU) ||
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(s->threshold && s->threshold!=64)) return AES_BAD_STATE;
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if (width!=4 || (off&3)) return AES_BAD_WIDTH;
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if (write) {
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if (*value>UINT32_MAX) return AES_BAD_VALUE;
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uint32_t v=(uint32_t)*value;
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switch (off) {
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case 8:
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if (v!=1 && v!=2) return AES_UNSUPPORTED;
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if (s->need) return AES_BAD_STATE;
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s->running=v==1;return AES_OK;
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case 0x18:
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if (v&~0x3efffU) return AES_BAD_VALUE;
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s->irq_status&=~v;return AES_OK;
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case 0x1c:
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if (v&~0x3efffU) return AES_BAD_VALUE;
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s->irq_enable=v;return AES_OK;
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case 0x20:
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if (v!=64) return AES_BAD_VALUE;
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s->threshold=v;return AES_OK;
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case 0x200:return word(s,m,v);
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default:return AES_UNKNOWN_REGISTER;
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}
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}
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switch (off) {
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case 0x0c:*value=s->need ? 0 : 0x3f80;return AES_OK;
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case 0x18:*value=s->irq_status;return AES_OK;
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case 0x1c:*value=s->irq_enable;return AES_OK;
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case 0x24:*value=2;return AES_OK; /* FIFO words are synchronously consumed. */
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case 0x30:*value=s->completed_tag;return AES_OK;
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default:return AES_UNKNOWN_REGISTER;
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}
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}
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int aes_engine_irq(const struct aes_engine *s)
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{ return s && s->ready==1 && (s->irq_status&s->irq_enable)!=0; }
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