Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
29 lines
1.2 KiB
C
29 lines
1.2 KiB
C
/* SPDX-License-Identifier: MIT */
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#pragma once
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#include "aes.h"
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#define AES_TRANSFER_MAX 0x100000U
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struct aes_slot { struct aes_key key; uint32_t valid,encrypt,mode; };
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struct aes_engine {
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uint32_t ready,running,irq_enable,threshold,irq_status,completed_tag;
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uint32_t header,words[8],used,need;
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struct aes_slot keys[2];
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uint8_t iv[4][16];
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uint32_t iv_valid;
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uint64_t commands,transfers,bytes,barriers,iv_exports;
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};
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/* map must validate a single guest IOVA-page fragment and return a stable
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* CPU-accessible mapping, never host MMIO. Serialize the whole transaction
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* against page-table/ownership changes. publish cannot fail. All mappings
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* are obtained and checked before any data or IV is changed. */
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struct aes_dma {
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void *ctx;
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volatile uint8_t *(*map)(void *ctx,uint64_t iova,size_t size,int write);
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void (*publish)(void *ctx,volatile uint8_t *memory,size_t size);
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};
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enum aes_result { AES_OK,AES_BAD_STATE,AES_BAD_WIDTH,AES_BAD_VALUE,AES_UNKNOWN_REGISTER,AES_UNSUPPORTED,AES_DMA_REFUSED };
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void aes_engine_init(struct aes_engine *s);
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enum aes_result aes_engine_access(struct aes_engine *s,const struct aes_dma *dma,
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uint64_t offset,unsigned width,int write,uint64_t *value);
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int aes_engine_irq(const struct aes_engine *s);
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