Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
104 lines
4.1 KiB
C
104 lines
4.1 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "aic.h"
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int aic_config_valid(const struct aic_config *config)
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{
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return config && config->irqs && config->irqs <= AIC_MAX_IRQS &&
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!(config->irqs & 31) && config->revision == 0xa &&
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config->event >= 0x14a00 && !(config->event & 3);
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}
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int aic_pending(const struct aic_config *config, const struct aic_state *state)
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{
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if (!aic_config_valid(config) || !state || !(state->control & 1)) return 0;
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for (unsigned i=0; i<config->irqs/32; i++)
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if (state->unmasked[i] & (state->software[i] | state->level[i])) return 1;
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return 0;
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}
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enum aic_result aic_set_level(const struct aic_config *config,
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struct aic_state *state, unsigned irq, int level)
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{
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if (!aic_config_valid(config) || !state) return AIC_BAD_CONFIG;
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if (irq >= config->irqs || (level != 0 && level != 1)) return AIC_BAD_VALUE;
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uint32_t bit = UINT32_C(1) << (irq & 31);
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if (level) state->level[irq/32] |= bit;
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else state->level[irq/32] &= ~bit;
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return AIC_OK;
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}
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static uint32_t acknowledge(const struct aic_config *config, struct aic_state *state)
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{
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if (!(state->control & 1)) return 0;
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for (unsigned i=0; i<config->irqs/32; i++) {
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uint32_t pending = state->unmasked[i] & (state->software[i] | state->level[i]);
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if (!pending) continue;
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unsigned bit = (unsigned)__builtin_ctz(pending);
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uint32_t mask = UINT32_C(1) << bit;
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/* EVENT auto-masks the source and consumes its software request.
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* A physical/virtual producer's level remains until it deasserts.
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* Darwin completes delivery with MASK_CLR, not a separate EOI token. */
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state->unmasked[i] &= ~mask;
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state->software[i] &= ~mask;
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state->events++;
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return UINT32_C(0x10000) | (i*32 + bit); /* die 0, hardware type 1 */
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}
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return 0;
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}
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enum aic_result aic_access(const struct aic_config *config,
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struct aic_state *state, uint64_t offset, unsigned width, int write,
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uint64_t *value)
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{
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if (!aic_config_valid(config) || !value) return AIC_BAD_CONFIG;
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if (width != 4 || (offset & 3)) return AIC_BAD_WIDTH;
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if (offset == 0 || offset == 4 || offset == 12) {
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if (write) return AIC_READ_ONLY;
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*value = offset == 0 ? config->revision : offset == 4 ? config->irqs :
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UINT32_C(0x01001000); /* capacity: one die, 4096 IRQ slots */
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return AIC_OK;
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}
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if (!state) return AIC_BAD_CONFIG;
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if (offset == config->event) {
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if (write) return AIC_READ_ONLY;
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*value = acknowledge(config, state);
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return AIC_OK;
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}
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if (offset == 0x14) {
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if (write) {
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if (*value & ~UINT64_C(1)) return AIC_BAD_VALUE;
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state->control = (uint32_t)*value;
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} else *value = state->control;
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return AIC_OK;
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}
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if (offset >= 0x10000 && offset < 0x14000) {
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unsigned irq = (unsigned)((offset-0x10000)/4);
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if (irq >= config->irqs) return AIC_UNKNOWN_REGISTER;
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/* This virtual controller routes to its single cluster. Delayed
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* delivery groups, other targets and reserved bits need new backends. */
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if (write && *value) return AIC_BAD_VALUE;
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if (!write) *value = 0;
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return AIC_OK;
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}
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if (offset >= 0x14000 && offset < 0x14a00) {
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unsigned bank = (unsigned)((offset-0x14000)/0x200);
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unsigned word = (unsigned)((offset & 0x1ff)/4);
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uint32_t valid = word < config->irqs/32 ? UINT32_MAX : 0;
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if (write) {
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if (bank == 4) return AIC_READ_ONLY;
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if (*value > UINT32_MAX) return AIC_BAD_VALUE;
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uint32_t bits = (uint32_t)*value & valid;
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if (bank == 0) state->software[word] |= bits;
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else if (bank == 1) state->software[word] &= ~bits;
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else if (bank == 2) state->unmasked[word] &= ~bits;
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else state->unmasked[word] |= bits;
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} else {
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if (bank < 2) *value = state->software[word] & valid;
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else if (bank < 4) *value = ~state->unmasked[word];
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else *value = state->level[word] & valid;
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}
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return AIC_OK;
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}
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return AIC_UNKNOWN_REGISTER;
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}
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