Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
30 lines
1.3 KiB
C
30 lines
1.3 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "cpu-release.h"
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int guest_cpu_release_write(struct guest_cpu_release *s,uint64_t allowed,
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uint64_t offset,unsigned width,uint64_t value,
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int (*launch)(void *,unsigned),void *context)
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{
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if (!s || !launch || width!=4 || !allowed || allowed&~UINT64_C(0x3e) ||
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s->armed&~allowed || s->issued&~s->armed ||
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(offset!=4 && offset!=8 && offset!=12)) return 0;
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if (!value) return 1; /* the stock loop also writes zero to an idle cluster */
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if (value&(value-1)) return 0;
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/* The global bitmap is packed E0..E3,P0..P1. Cluster registers are
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* local bitmaps: +8 selects E0..E3; +12 selects P0..P1. The stock PMGR
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* loop masks the cluster width, then shifts by that width for the next
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* register. Never interpret a P-local bit as the same numbered E core. */
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uint64_t global=value;
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if (offset==8 && (value&~UINT64_C(0xf))) return 0;
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if (offset==12) {
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if (value&~UINT64_C(3)) return 0;
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global=value<<4;
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}
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if (global&~allowed) return 0;
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if (offset==4) { s->armed|=global;return 1; }
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if (!(s->armed&global) || (s->issued&global)) return 0;
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unsigned slot=(unsigned)__builtin_ctzll(global);
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if (!launch(context,slot)) return 0;
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s->issued|=global;
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return 1;
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}
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