Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
14 lines
642 B
C
14 lines
642 B
C
/* SPDX-License-Identifier: MIT */
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#ifndef SNAP_CPU_RUNTIME_H
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#define SNAP_CPU_RUNTIME_H
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#include "cpu.h"
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#define GUEST_RUNTIME_PAGE UINT64_C(0x1000)
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#define GUEST_RUNTIME_STACK UINT64_C(0x10000)
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struct guest_cpu_storage { uint64_t vncr, output, stack_low, stack_high; };
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/* Plan one VNCR per CPU and output/stack storage for each secondary before
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* publishing any pointer. CPU0 retains its caller stack/output. Failure leaves
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* the plan and end unchanged. The caller zeros and owns the allocated range. */
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int guest_cpu_storage_plan(uint64_t begin, uint64_t limit,
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struct guest_cpu_storage out[GUEST_CPU_COUNT], uint64_t *end);
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#endif
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