Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
194 lines
7.4 KiB
C
194 lines
7.4 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "dart.h"
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#define PA_LIMIT (1UL<<36)
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#define VA_LIMIT (1UL<<44)
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#define PTE_ADDRESS 0x0000003ffffffc00UL
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#define ERROR_FLAG (1U<<31)
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/* Pinned j700 normal SEP stream windows. The native SPTM uses a level1
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* root for these biased IOVAs; the 1 TiB tag is outside both table indices. */
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int dart_sep_iova_range(unsigned sid,uint64_t iova,uint64_t size)
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{
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if (sid>1 || !size) return 0;
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uint64_t low=sid ? 0x10000000000UL : 0x10000004000UL;
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uint64_t end=sid ? 0x10050000000UL : 0x100ffff4000UL;
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return iova>=low && iova<end && size<=end-iova;
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}
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void dart_init(struct dart_state *s)
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{
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if (!s) return;
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volatile uint8_t *p=(volatile uint8_t *)s;
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for (unsigned i=0; i<sizeof(*s); i++) p[i]=0;
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}
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static uint32_t stream_mask(unsigned streams, unsigned bank)
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{
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unsigned start=bank*32;
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if (start>=streams) return 0;
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return streams-start>=32 ? UINT32_MAX : (1U<<(streams-start))-1;
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}
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int dart_irq_pending(const struct dart_state *s)
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{
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return s && (s->error & ERROR_FLAG) && (s->error & ~s->error_mask & 0x20007fffU);
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}
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enum dart_result dart_access(struct dart_state *s, unsigned streams,
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uint64_t off, unsigned width, int write, uint64_t *value)
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{
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if (!s || !value || !streams || streams>DART_STREAMS) return DART_BAD_CONFIG;
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if (width!=4 || (off&3)) return DART_BAD_WIDTH;
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if (write && *value>UINT32_MAX) return DART_BAD_VALUE;
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uint32_t v=(uint32_t)*value;
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if (off<0x10) {
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if (write) return DART_READ_ONLY;
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/* 16 KiB pages with subpage protection, zero cached translations,
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* full bypass, 36-bit PA / 44-bit VA, v2 register layout. */
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const uint32_t params[]={0x8e000000,1,(36U<<24)|(44U<<16)|(2U<<8),
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(streams<<16)|streams};
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*value=params[off/4];
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return DART_OK;
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}
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if (off==0x80) {
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if (!write) { *value=s->tlb_op; return DART_OK; }
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unsigned op=(v>>8)&7, sid=v&255;
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if ((v & ~0x8000f7ffU) || (op!=0 && op!=1 && op!=4) ||
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(op==1 && sid>=streams) || (op!=1 && sid) ||
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((v&(1U<<14)) && s->tlb_start>s->tlb_end)) return DART_BAD_VALUE;
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/* Every walk reads current guest tables and completes synchronously.
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* There is no cached entry or in-flight translation left to drain. */
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s->tlb_op=v & ~ERROR_FLAG;
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s->flushes++;
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return DART_OK;
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}
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if (off==0x98 || off==0xa0) {
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uint32_t *reg=off==0x98 ? &s->tlb_start : &s->tlb_end;
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if (write) { if (v&3) return DART_BAD_VALUE; *reg=v; }
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else *value=*reg;
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return DART_OK;
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}
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if (off==0x100) {
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if (write) { if (v&ERROR_FLAG) s->error=0; }
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else *value=s->error;
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return DART_OK;
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}
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if (off==0x104) {
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if (write) s->error_mask=v;
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else *value=s->error_mask;
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return DART_OK;
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}
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if (off==0x170 || off==0x174) {
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if (write) return DART_READ_ONLY;
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*value=(uint32_t)(s->error_address>>(off==0x174 ? 32 : 0));
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return DART_OK;
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}
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if (off>=0x1c0 && off<0x1e0) {
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unsigned bank=(unsigned)(off-0x1c0)/4;
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if (write) s->error_streams[bank]&=~v;
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else *value=s->error_streams[bank];
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return DART_OK;
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}
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if (off==0x200 || off==0x204 || off==0x208) {
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if (!write) { *value=off==0x208 ? s->protect_lock : s->protect; return DART_OK; }
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if (v&~0x1fU) return DART_BAD_VALUE;
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if (off==0x200) s->protect|=v;
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else if (off==0x204) s->protect&=~(v&~s->protect_lock);
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else s->protect_lock|=v;
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return DART_OK;
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}
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/* This uncached virtual DART has no TLIMIT allocation or saved cache
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* diagnostics. POWERUP's initial values are all zero. */
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if (off==0x210 || off==0x228 || off==0x22c) {
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if (write) return off==0x210 && !v ? DART_OK : DART_READ_ONLY;
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*value=0;
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return DART_OK;
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}
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if (off>=0xc00 && off<0xc40) {
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unsigned bank=(unsigned)(off&0x1f)/4;
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if (!write) *value=s->enabled[bank];
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else if (off<0xc20) s->enabled[bank]|=v&stream_mask(streams,bank);
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else s->enabled[bank]&=~v;
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return DART_OK;
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}
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if (off>=0x1000 && off<0x1800) {
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unsigned sid=(unsigned)(off&0x3ff)/4;
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if (sid>=streams) return DART_UNKNOWN_REGISTER;
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uint32_t *reg=off<0x1400 ? &s->tcr[sid] : &s->ttbr[sid];
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if (!write) { *value=*reg; return DART_OK; }
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if (s->protect&1) return DART_BAD_VALUE;
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if (off<0x1400) {
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/* Remapping and other unaudited modes remain refused. */
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if ((v&~15U) || (v&3)==3) return DART_BAD_VALUE;
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} else if ((v&~0x3ffffffdU) || ((uint64_t)(v&0x3ffffffcU)<<12)>=PA_LIMIT)
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return DART_BAD_VALUE;
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*reg=v;
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return DART_OK;
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}
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return DART_UNKNOWN_REGISTER;
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}
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static enum dart_result fault(struct dart_state *s,unsigned sid,uint64_t iova,
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int write,uint32_t code)
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{
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s->faults++;
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s->error_streams[sid/32]|=1U<<(sid%32);
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if (!(s->error&ERROR_FLAG)) {
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s->error=ERROR_FLAG | (write ? 1U<<28 : 0) | (sid<<20) | code;
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s->error_address=iova;
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} else s->error|=1U<<19;
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return DART_FAULT;
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}
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enum dart_result dart_translate(struct dart_state *s,unsigned streams,
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const struct dart_memory *m,unsigned sid,uint64_t iova,uint64_t size,
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int write,uint64_t *physical)
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{
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if (!s || !m || !m->read64 || !m->allow || !physical || !streams ||
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streams>DART_STREAMS || sid>=streams || !size || size>0x4000 ||
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(iova&0x3fff)>0x4000-size || (write!=0 && write!=1)) return DART_BAD_CONFIG;
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if (iova>=VA_LIMIT || size>VA_LIMIT-iova)
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return fault(s,sid,iova,write,1U<<6);
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uint32_t tcr=s->tcr[sid];
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if (!(s->enabled[sid/32]&(1U<<(sid%32))) || !(tcr&3) || (tcr&3)==3)
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return fault(s,sid,iova,write,1U);
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uint64_t pa;
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if (tcr&2) pa=iova;
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else {
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if (!(s->ttbr[sid]&1)) return fault(s,sid,iova,write,1U);
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if (!(tcr&8)) {
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int sep=s->initialized_ids==(1U<<20) && s->powered_ids==(1U<<20);
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if (sep ? !dart_sep_iova_range(sid,iova,size) : iova>=(1UL<<36))
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return fault(s,sid,iova,write,1U<<6);
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}
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pa=(uint64_t)(s->ttbr[sid]&0x3ffffffcU)<<12;
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uint64_t seen[3]; unsigned count=0;
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for (unsigned shift=tcr&8 ? 36 : 25; ; shift-=11) {
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for (unsigned j=0; j<count; j++)
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if (seen[j]==pa) return fault(s,sid,iova,write,1U<<7);
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seen[count++]=pa;
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uint64_t pte;
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if (pa>=PA_LIMIT || 0x4000>PA_LIMIT-pa || !m->allow(m->ctx,pa,0x4000,0) ||
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m->read64(m->ctx,pa+8*((iova>>shift)&2047),&pte))
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return fault(s,sid,iova,write,1U<<7);
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if (!(pte&1)) return fault(s,sid,iova,write,1U<<(shift==14 ? 3 : shift==25 ? 2 : 1));
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pa=(pte&PTE_ADDRESS)<<4;
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if (shift==14) {
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if (pte & (write ? 4U : 8U)) return fault(s,sid,iova,write,1U<<(write ? 4 : 5));
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uint64_t begin=((pte>>52)&0xfff)*4, end=(((pte>>40)&0xfff)+1)*4;
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uint64_t offset=iova&0x3fff;
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if (offset<begin || offset>=end || size>end-offset)
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return fault(s,sid,iova,write,1U<<29);
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pa+=offset;
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break;
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}
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}
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}
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if (pa>=PA_LIMIT || size>PA_LIMIT-pa || !m->allow(m->ctx,pa,size,write))
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return fault(s,sid,iova,write,1U<<6);
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*physical=pa;
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s->translations++;
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return DART_OK;
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}
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