Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
96 lines
3.3 KiB
C
96 lines
3.3 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "exception.h"
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int exception_vector_step(uint64_t syndrome, uint64_t pc, uint64_t vbar)
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{
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return (syndrome >> 26) == 0x32 && vbar && !(vbar & 0x7ff) &&
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pc >= vbar && pc - vbar < 0x800 && !((pc - vbar) & 0x7f);
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}
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void exception_step_set(struct exception_step *step, int on,
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uint64_t *spsr, uint64_t *mdscr)
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{
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const uint64_t d = 1UL << 9, ss = 1UL << 21;
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if (on) {
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if (!step->active) step->saved_d = *spsr & d;
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step->active = 1;
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*spsr = (*spsr | ss) & ~d;
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*mdscr |= 1;
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} else {
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*spsr &= ~ss;
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*mdscr &= ~1UL;
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if (step->active) *spsr = (*spsr & ~d) | step->saved_d;
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step->active = 0;
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}
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}
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int exception_step_fiq(const struct exception_step *step, int pending)
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{
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return pending && !step->active;
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}
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int exception_step_suspend(struct exception_step *step, uint64_t *guest_spsr)
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{
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if (!step->active) return 0;
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*guest_spsr = (*guest_spsr & ~((1UL << 9) | (1UL << 21))) | step->saved_d;
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step->active = 0;
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return 1;
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}
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int exception_kernel_page_fault(uint64_t esr)
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{
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unsigned ec = (esr >> 26) & 63, fsc = esr & 63;
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return (ec == 0x21 || ec == 0x25) && fsc >= 4 && fsc <= 15;
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}
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int exception_user_return(uint32_t instruction, uint64_t virtual_hcr,
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uint64_t pc, uint64_t guest_spsr, uint64_t *physical_spsr)
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{
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const uint64_t host_bits = (1UL << 34) | (1UL << 31) | (1UL << 27);
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if (!physical_spsr || instruction != 0xd69f03e0U ||
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(virtual_hcr & host_bits) != host_bits || !pc || pc >= (1UL << 47) ||
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(pc & 3) || (guest_spsr & 31) || (guest_spsr >> 32) ||
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(guest_spsr & ((1UL << 20) | (1UL << 5)))) return 0;
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*physical_spsr = guest_spsr;
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return 1;
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}
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int exception_user_sync(uint64_t vector, uint64_t saved_spsr, uint64_t esr)
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{
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unsigned ec = (esr >> 26) & 63, fsc = esr & 63;
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return vector == 0x400 && !(saved_spsr & 31) &&
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(ec == 0x15 || ((ec == 0x20 || ec == 0x24) && fsc >= 4 && fsc <= 15));
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}
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int exception_monitor_origin(uint64_t pc, uint64_t physical_spsr)
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{
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unsigned mode = physical_spsr & 31;
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return pc >= 0xffff800000000000UL && !(pc & 3) && (mode == 4 || mode == 5);
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}
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int exception_user_step(uint32_t instruction, uint64_t entry, uint64_t stack,
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uint64_t esr, uint64_t spsr, uint64_t pc, uint64_t x0, uint64_t sp)
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{
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return instruction == 0x910003e0U && entry && entry < (1UL << 47) - 4 &&
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!(entry & 3) && stack && stack < (1UL << 47) &&
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(esr >> 26) == 0x32 && !(spsr & 31) && pc == entry + 4 &&
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x0 == stack && sp == stack;
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}
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int exception_kernel_return(uint32_t instruction, uint64_t virtual_hcr,
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uint64_t pc, uint64_t guest_spsr, uint64_t *physical_spsr)
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{
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const uint64_t host_bits = (1UL << 34) | (1UL << 31) | (1UL << 27);
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unsigned mode = guest_spsr & 31;
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if (!physical_spsr || instruction != 0xd69f03e0U ||
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(virtual_hcr & host_bits) != host_bits ||
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pc < 0xffff800000000000UL || (pc & 3) ||
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(mode != 8 && mode != 9) || (guest_spsr >> 32) ||
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(guest_spsr & ((1UL << 20) | (1UL << 5))))
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return 0;
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/* NV reports EL2 in the saved mode; the kernel actually executes at
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* physical EL1. Preserve NZCV, DAIF, PAN and the stack selector. */
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*physical_spsr = (guest_spsr & ~15UL) | (mode - 4);
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return 1;
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}
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