Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
36 lines
2.1 KiB
C
36 lines
2.1 KiB
C
/* SPDX-License-Identifier: MIT */
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#pragma once
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#include <stdint.h>
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/* Translate a plain ERET to the nested host kernel. Other privilege regimes,
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* authenticated ERET and illegal return states require separate adapters. */
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int exception_kernel_return(uint32_t instruction, uint64_t virtual_hcr,
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uint64_t pc, uint64_t guest_spsr, uint64_t *physical_spsr);
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/* EL0 keeps its real privilege level under NV. The caller must additionally
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* validate the active user address space before installing this state. */
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int exception_user_return(uint32_t instruction, uint64_t virtual_hcr,
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uint64_t pc, uint64_t guest_spsr, uint64_t *physical_spsr);
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int exception_user_sync(uint64_t vector, uint64_t saved_spsr, uint64_t esr);
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int exception_monitor_origin(uint64_t pc, uint64_t physical_spsr);
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/* Narrow execution witness: the reached entry starts with MOV X0, SP.
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* A return request alone, a vector landing, or a failed instruction is not
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* evidence that this instruction completed at physical EL0. */
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int exception_user_step(uint32_t instruction, uint64_t entry, uint64_t stack,
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uint64_t esr, uint64_t spsr, uint64_t pc, uint64_t x0, uint64_t sp);
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/* These are delivered to XNU's handler in normal runs. It decides whether
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* to resolve the fault or panic; other exceptions remain diagnostic stops. */
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int exception_kernel_page_fault(uint64_t esr);
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struct exception_step { uint64_t active, saved_d; };
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/* Repeated enable must not replace the original guest D bit with our temporary
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* zero. Disable when idle must not write a stale D bit into a new context. */
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void exception_step_set(struct exception_step *step, int on,
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uint64_t *spsr, uint64_t *mdscr);
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int exception_step_fiq(const struct exception_step *step, int pending);
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/* A synchronous guest exception can still interrupt a stepped instruction.
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* Remove monitor-only bits from its saved context before XNU reads it. */
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int exception_step_suspend(struct exception_step *step, uint64_t *guest_spsr);
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/* A stepped exception lands at an architectural vector slot, not at an
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* arbitrary instruction later in the same executable page. */
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int exception_vector_step(uint64_t syndrome, uint64_t pc, uint64_t vbar);
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