Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
83 lines
3.4 KiB
C
83 lines
3.4 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "mmio.h"
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int mmio_ldp64_decode(uint32_t instruction, uint64_t esr,
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const uint64_t regs[31], uint64_t sp, struct mmio_pair *out)
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{
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const uint64_t syndrome_mask = (0x3fUL << 26) | (1UL << 25) |
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(1UL << 24) | (0x1fUL << 6); /* ISV, FnV, EA, CM, S1PTW, WnR */
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if (!regs || !out ||
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(esr & syndrome_mask) != ((0x24UL << 26) | (1UL << 25)) ||
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((esr & 0x3c) != 4 && (esr & 0x3c) != 12) ||
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(instruction & 0xffc00000U) != 0xa9400000U) return 0;
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unsigned first=instruction & 31, second=(instruction >> 10) & 31;
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unsigned base=(instruction >> 5) & 31;
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if (first == second) return 0; /* Constrained-unpredictable overlap. */
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int immediate=(int)((instruction >> 15) & 127);
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if (immediate & 64) immediate -= 128;
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uint64_t address=(base == 31 ? sp : regs[base]) + (uint64_t)(immediate * 8);
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/* A pair crossing the address-space boundary cannot be one device entry. */
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if ((address & 7) || address > UINT64_MAX-15) return 0;
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*out=(struct mmio_pair){address, {first, second}};
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return 1;
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}
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void mmio_ldp64_complete(const struct mmio_pair *pair,
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const uint64_t values[2], uint64_t regs[31])
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{
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if (pair->reg[0] != 31) regs[pair->reg[0]]=values[0];
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if (pair->reg[1] != 31) regs[pair->reg[1]]=values[1];
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}
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int mmio_stp64_decode(uint32_t instruction, uint64_t esr,
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const uint64_t regs[31], uint64_t sp, struct mmio_pair *out)
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{
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const uint64_t syndrome_mask=(0x3fUL<<26)|(1UL<<25)|(1UL<<24)|(0x1fUL<<6);
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if (!regs || !out ||
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(esr&syndrome_mask)!=((0x24UL<<26)|(1UL<<25)|(1UL<<6)) ||
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((esr&0x3c)!=4 && (esr&0x3c)!=12) ||
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(instruction&0xffc00000U)!=0xa9000000U) return 0;
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unsigned base=(instruction>>5)&31;
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if (base==31 && (sp&15)) return 0;
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int immediate=(instruction>>15)&127;
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if (immediate&64) immediate-=128;
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immediate*=8;
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uint64_t original=base==31 ? sp : regs[base];
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if ((immediate<0 && original<(uint64_t)-immediate) ||
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(immediate>0 && original>UINT64_MAX-(uint64_t)immediate)) return 0;
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uint64_t address=original+(uint64_t)immediate;
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if ((address&7) || address>UINT64_MAX-15) return 0;
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*out=(struct mmio_pair){address,{instruction&31,(instruction>>10)&31}};
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return 1;
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}
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int mmio_ldr32_pre_decode(uint32_t instruction, uint64_t esr,
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const uint64_t regs[31], uint64_t sp, struct mmio_preload *out)
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{
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const uint64_t syndrome_mask=(0x3fUL<<26)|(1UL<<25)|(1UL<<24)|(0x1fUL<<6);
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if (!regs || !out ||
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(esr&syndrome_mask)!=((0x24UL<<26)|(1UL<<25)) ||
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((esr&0x3c)!=4 && (esr&0x3c)!=12) ||
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(instruction&0xffe00c00U)!=0xb8400c00U) return 0;
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unsigned reg=instruction&31, base=(instruction>>5)&31;
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if (reg==base && base!=31) return 0;
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if (base==31 && (sp&15)) return 0;
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int immediate=(instruction>>12)&511;
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if (immediate&256) immediate-=512;
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uint64_t original=base==31 ? sp : regs[base];
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if ((immediate<0 && original<(uint64_t)-immediate) ||
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(immediate>0 && original>UINT64_MAX-(uint64_t)immediate)) return 0;
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uint64_t address=original+(uint64_t)immediate;
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if ((address&3) || address>UINT64_MAX-3) return 0;
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*out=(struct mmio_preload){address,reg,base};
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return 1;
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}
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void mmio_ldr32_pre_complete(const struct mmio_preload *load, uint32_t value,
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uint64_t regs[31], uint64_t *sp)
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{
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if (load->reg!=31) regs[load->reg]=value;
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if (load->base==31) *sp=load->address;
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else regs[load->base]=load->address;
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}
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