Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
93 lines
3.9 KiB
C
93 lines
3.9 KiB
C
/* SPDX-License-Identifier: MIT */
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#ifndef SNAP_NATIVE_WRITER_DEBUG_H
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#define SNAP_NATIVE_WRITER_DEBUG_H
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#include "native-writer.h"
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#define NATIVE_WRITER_BCR UINT64_C(0x1e3)
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#define NATIVE_WRITER_MDSCR UINT64_C(0xa000)
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/* Per physical CPU. Saved state is retained for post-stop comparison. */
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struct native_writer_debug {
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uint64_t saved_value[6],saved_control[6];
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uint64_t observed_value[6],observed_control[6];
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uint64_t dfr0,saved,installed,install_verified,restores,restore_failed;
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uint64_t traps,rejected,stepped,last_pc,last_word;
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};
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_Static_assert(sizeof(struct native_writer_debug)==280,"writer debug capture ABI");
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struct native_writer_debug_ops {
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uint64_t (*read)(void *ctx,unsigned index,int control);
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void (*write)(void *ctx,unsigned index,int control,uint64_t value);
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void (*barrier)(void *ctx);
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void *ctx;
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};
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static inline int native_writer_debug_ops_valid(const struct native_writer_debug_ops *o)
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{return o && o->read && o->write && o->barrier;}
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/* Disable the whole bank before changing any address. Restore every register
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* even if a prior readback fails; the caller must preserve failed qualification. */
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static inline int native_writer_debug_restore(struct native_writer_debug *s,
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const struct native_writer_debug_ops *o)
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{
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if(!s || !native_writer_debug_ops_valid(o))return 0;
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if(!s->saved)return 1;
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for(unsigned i=0;i<6;i++)o->write(o->ctx,i,1,0);
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o->barrier(o->ctx);
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int ok=1;
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for(unsigned i=0;i<6;i++)ok &= o->read(o->ctx,i,1)==0;
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for(unsigned i=0;i<6;i++)o->write(o->ctx,i,0,s->saved_value[i]);
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o->barrier(o->ctx);
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for(unsigned i=0;i<6;i++)o->write(o->ctx,i,1,s->saved_control[i]);
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o->barrier(o->ctx);
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for(unsigned i=0;i<6;i++) {
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s->observed_value[i]=o->read(o->ctx,i,0);
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s->observed_control[i]=o->read(o->ctx,i,1);
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ok &= s->observed_value[i]==s->saved_value[i] &&
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s->observed_control[i]==s->saved_control[i];
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}
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s->installed=0;s->restores++;
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if(!ok)s->restore_failed++;
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return ok;
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}
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/* armed: one bit per writer site whose comparator is enabled. A site left
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* unarmed keeps its address with a zero control word, and is verified so;
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* every site's terminal write must then be covered some other way
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* (SNAP_ERET_SNAPSHOT for site 5). */
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#define NATIVE_WRITER_ARMED_ALL ((1u<<NATIVE_WRITER_SITE_COUNT)-1)
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static inline int native_writer_debug_install_armed(struct native_writer_debug *s,
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const struct native_writer_debug_ops *o,uint64_t dfr0,unsigned armed)
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{
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if(!s || !native_writer_debug_ops_valid(o) || s->saved || !armed ||
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(armed&~NATIVE_WRITER_ARMED_ALL))return 0;
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s->dfr0=dfr0;
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unsigned version=dfr0&15;
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if(version<6 || version>11 || ((dfr0>>12)&15)<5)return 0;
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for(unsigned i=0;i<6;i++) {
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s->saved_value[i]=o->read(o->ctx,i,0);
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s->saved_control[i]=o->read(o->ctx,i,1);
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}
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s->saved=1;
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for(unsigned i=0;i<6;i++)o->write(o->ctx,i,1,0);
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o->barrier(o->ctx);
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int disabled=1;
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for(unsigned i=0;i<6;i++)disabled &= o->read(o->ctx,i,1)==0;
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if(!disabled) {native_writer_debug_restore(s,o);return 0;}
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for(unsigned i=0;i<6;i++)o->write(o->ctx,i,0,native_writer_sites[i].va);
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o->barrier(o->ctx);
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for(unsigned i=0;i<6;i++)o->write(o->ctx,i,1,(armed>>i)&1 ? NATIVE_WRITER_BCR : 0);
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o->barrier(o->ctx);
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int ok=1;
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for(unsigned i=0;i<6;i++) {
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s->observed_value[i]=o->read(o->ctx,i,0);
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s->observed_control[i]=o->read(o->ctx,i,1);
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ok &= s->observed_value[i]==native_writer_sites[i].va &&
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s->observed_control[i]==((armed>>i)&1 ? NATIVE_WRITER_BCR : 0);
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}
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if(!ok) {native_writer_debug_restore(s,o);return 0;}
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s->installed=s->install_verified=1;
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return 1;
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}
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static inline int native_writer_debug_install(struct native_writer_debug *s,
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const struct native_writer_debug_ops *o,uint64_t dfr0)
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{return native_writer_debug_install_armed(s,o,dfr0,NATIVE_WRITER_ARMED_ALL);}
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#endif
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