Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
214 lines
4.3 KiB
ArmAsm
214 lines
4.3 KiB
ArmAsm
// SPDX-License-Identifier: MIT
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.arch_extension pauth
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.text
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.balign 4
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#ifndef PAUTH_NATIVE_NAME
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#define PAUTH_NATIVE_NAME pauth_native_user
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#endif
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.globl PAUTH_NATIVE_NAME
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PAUTH_NATIVE_NAME:
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stp x29,x30,[sp,#-96]!
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stp x19,x20,[sp,#16]
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stp x21,x22,[sp,#32]
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stp x23,x24,[sp,#48]
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stp x25,x26,[sp,#64]
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stp x27,x28,[sp,#80]
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mov x19,x0
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mov x20,x1
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mov w0,#1
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cbz x19,.Lreturn
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cbz x20,.Lreturn
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mrs x9,CurrentEL
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cmp x9,#8
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b.ne .Lreturn
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mrs x9,hcr_el2
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tbnz x9,#34,.Lreturn // only the non-VHE EL2 regime
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mrs x22,sctlr_el2
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tbz x22,#0,.Lreturn
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mrs x23,tcr_el2
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ubfx x9,x23,#14,#2
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cbnz x9,.Lreturn // 4K EL2 translation only
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and x9,x23,#63
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cmp x9,#17
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b.lo .Lreturn
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cmp x9,#24
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b.hi .Lreturn // preserve the existing L0 table geometry
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mrs x9,id_aa64isar1_el1
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ubfx x10,x9,#4,#8
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mrs x9,id_aa64isar2_el1
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ubfx x9,x9,#12,#4
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orr x9,x9,x10
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cbz x9,.Lreturn
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ldr x26,[x19,#32]
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cmp x26,#3
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b.hi .Lreturn
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ldp x10,x11,[x19,#40]
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orr x9,x10,x11
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cmp x9,#1
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b.hi .Lreturn
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#if !PAUTH_NATIVE_RAW_SIGN
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// Only canonical lower 47-bit pointers can round-trip through AUT.
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// A top-byte tag is legal only when TBI applies to this key class.
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cmp x26,#2
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cset x12,hs
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eor x13,x11,#1
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orr x12,x12,x13
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and x12,x12,x10
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ldr x13,[x19]
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cbnz x12,.Ltagged_pointer
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lsr x13,x13,#47
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b .Lcheck_pointer
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.Ltagged_pointer:
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ubfx x13,x13,#47,#9
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.Lcheck_pointer:
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cbnz x13,.Lreturn
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#endif
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// Expanding T0SZ within L0 preserves all currently mapped EL2 VAs.
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// TBI/TBID affect PAC composition; the executing identity mappings are
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// untagged. Scope the changes to this PE and flush its EL2 TLB both ways.
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mov x9,x23
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mov x12,#17
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bfi x9,x12,#0,#6
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bfi x9,x10,#20,#1
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bfi x9,x11,#29,#1
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mrs x21,daif
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msr daifset,#15
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dsb sy
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msr tcr_el2,x9
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isb
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tlbi alle2
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dsb sy
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isb
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mov x9,#0x2000
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movk x9,#0xc800,lsl #16
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orr x9,x22,x9
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msr sctlr_el2,x9
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isb
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ldp x27,x28,[x19,#16]
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cbz x26,.Lia_save
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cmp x26,#1
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b.eq .Lib_save
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cmp x26,#2
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b.eq .Lda_save
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mrs x24,s3_0_c2_c2_2
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mrs x25,s3_0_c2_c2_3
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msr s3_0_c2_c2_2,x27
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msr s3_0_c2_c2_3,x28
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b .Loperate
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.Lia_save:
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mrs x24,s3_0_c2_c1_0
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mrs x25,s3_0_c2_c1_1
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msr s3_0_c2_c1_0,x27
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msr s3_0_c2_c1_1,x28
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b .Loperate
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.Lib_save:
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mrs x24,s3_0_c2_c1_2
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mrs x25,s3_0_c2_c1_3
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msr s3_0_c2_c1_2,x27
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msr s3_0_c2_c1_3,x28
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b .Loperate
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.Lda_save:
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mrs x24,s3_0_c2_c2_0
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mrs x25,s3_0_c2_c2_1
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msr s3_0_c2_c2_0,x27
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msr s3_0_c2_c2_1,x28
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.Loperate:
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isb
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ldp x8,x9,[x19]
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cbz x26,.Lia_op
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cmp x26,#1
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b.eq .Lib_op
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cmp x26,#2
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b.eq .Lda_op
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pacdb x8,x9
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#if PAUTH_NATIVE_RAW_SIGN
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mov x10,xzr
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#else
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mov x10,x8
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autdb x10,x9
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#endif
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msr s3_0_c2_c2_2,x24
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msr s3_0_c2_c2_3,x25
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isb
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mrs x11,s3_0_c2_c2_2
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mrs x12,s3_0_c2_c2_3
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b .Lrestore
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.Lia_op:
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pacia x8,x9
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#if PAUTH_NATIVE_RAW_SIGN
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mov x10,xzr
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#else
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mov x10,x8
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autia x10,x9
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#endif
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msr s3_0_c2_c1_0,x24
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msr s3_0_c2_c1_1,x25
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isb
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mrs x11,s3_0_c2_c1_0
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mrs x12,s3_0_c2_c1_1
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b .Lrestore
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.Lib_op:
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pacib x8,x9
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#if PAUTH_NATIVE_RAW_SIGN
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mov x10,xzr
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#else
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mov x10,x8
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autib x10,x9
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#endif
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msr s3_0_c2_c1_2,x24
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msr s3_0_c2_c1_3,x25
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isb
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mrs x11,s3_0_c2_c1_2
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mrs x12,s3_0_c2_c1_3
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b .Lrestore
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.Lda_op:
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pacda x8,x9
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#if PAUTH_NATIVE_RAW_SIGN
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mov x10,xzr
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#else
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mov x10,x8
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autda x10,x9
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#endif
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msr s3_0_c2_c2_0,x24
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msr s3_0_c2_c2_1,x25
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isb
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mrs x11,s3_0_c2_c2_0
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mrs x12,s3_0_c2_c2_1
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.Lrestore:
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cmp x11,x24
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ccmp x12,x25,#0,eq
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cset x16,eq
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dsb sy
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msr tcr_el2,x23
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isb
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tlbi alle2
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dsb sy
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isb
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msr sctlr_el2,x22
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isb
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mrs x11,tcr_el2
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cmp x11,x23
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cset x12,eq
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orr x16,x16,x12,lsl #1
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mrs x11,sctlr_el2
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cmp x11,x22
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cset x12,eq
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orr x16,x16,x12,lsl #2
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msr daif,x21
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mrs x11,daif
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cmp x11,x21
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cset x12,eq
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orr x16,x16,x12,lsl #3
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stp x8,x10,[x20]
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str x16,[x20,#16]
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cmp x16,#15
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cset w0,ne
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.Lreturn:
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ldp x19,x20,[sp,#16]
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ldp x21,x22,[sp,#32]
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ldp x23,x24,[sp,#48]
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ldp x25,x26,[sp,#64]
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ldp x27,x28,[sp,#80]
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ldp x29,x30,[sp],#96
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ret
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