Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
41 lines
1.8 KiB
C
41 lines
1.8 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "pauth-pointer.h"
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static enum sptm_result fail(struct pauth_pointer_state *s,enum sptm_result r)
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{s->failures++;return r;}
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enum sptm_result pauth_pointer(uint64_t pointer,uint64_t key,uint64_t modifier,
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uint64_t authenticate,uint64_t tbi,uint64_t tbid,pauth_batch_sign_fn sign,
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void *ctx,struct pauth_pointer_state *s)
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{
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if(!s)return SPTM_BAD_CONFIG;
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s->attempts++;s->pointer=pointer;s->key=key;s->modifier=modifier;
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s->authenticate=authenticate;s->tbi=tbi;s->tbid=tbid;
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s->stripped=s->computed=s->result=0;
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if(!sign || authenticate>1 || tbi>1 || tbid>1 ||
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((uint32_t)key!=0 && (uint32_t)key!=2))return fail(s,SPTM_BAD_CONFIG);
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uint64_t tagged=tbi && ((uint32_t)key==2 || !tbid);
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uint64_t raw=pointer;
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if(authenticate) {
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/* XPAC restores PAC bits from address bit55. Our current user
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* geometry supports only canonical lower47-bit addresses. Upper
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* addresses are explicitly unsupported, never silently normalized. */
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if(pointer&(1ULL<<55))return fail(s,SPTM_BAD_ADDRESS);
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raw=pointer&((1ULL<<47)-1);
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if(tagged)raw|=pointer&0xff00000000000000ULL;
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}
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/* The original scalar SIGN service forwards every input bit to PAC.
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* The callback must be sign-only; noncanonical values need not round-trip. */
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s->stripped=raw;
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struct pauth_batch_entry entry={raw,modifier,(uint32_t)key,0};
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s->native_calls++;
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if(!sign(ctx,&entry,tbi,tbid,&s->computed))return fail(s,SPTM_SHADOW_FAILED);
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s->native_restores++;
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if(authenticate) {
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s->auths++;
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if(s->computed==pointer) {s->valid++;s->result=raw;}
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else {s->invalid++;s->result=UINT64_MAX;}
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} else {s->signs++;s->result=s->computed;}
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s->calls++;return SPTM_OK;
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}
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