Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
59 lines
2.3 KiB
C
59 lines
2.3 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "watchdog.h"
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void watchdog_init(struct watchdog_state *s, uint64_t now)
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{
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*s = (struct watchdog_state){.last = now, .ready = 1};
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}
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uint64_t watchdog_wait(struct watchdog_state *s, uint64_t now, uint64_t budget)
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{
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if (!s || !s->ready) return budget;
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uint64_t elapsed = now - s->last;
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/* Check before reducing the counter to 32 bits: even a late poll must
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* observe a threshold crossed before one or more counter wraps. */
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if ((s->control & 4) && (s->current >= s->bite ||
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elapsed >= (uint64_t)s->bite - s->current))
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s->reset = 1;
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s->current += (uint32_t)elapsed;
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s->last = now;
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if (s->reset) return 0;
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if (s->control & 4) {
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uint64_t left = (uint64_t)s->bite - s->current;
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if (left < budget) return left;
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}
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return budget;
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}
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enum watchdog_result watchdog_access(struct watchdog_state *s, uint64_t now,
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uint64_t offset, unsigned width, int write, uint64_t *value)
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{
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if (!s || !s->ready || !value) return WATCHDOG_BAD_STATE;
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if (width != 4 || (offset & 3)) return WATCHDOG_BAD_WIDTH;
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if (offset == 0x0c) {
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/* AppleARMWatchdogTimer::start disables WD0 even with wdt=-1.
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* This virtual channel has never been enabled and has no pending
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* interrupt. Admit disable and W1C status clear only. */
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if (write && (*value & ~2UL)) return WATCHDOG_BAD_VALUE;
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watchdog_wait(s, now, UINT64_MAX);
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if (!write) *value = 0;
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return WATCHDOG_OK;
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}
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if (offset != 0x10 && offset != 0x14 && offset != 0x1c)
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return WATCHDOG_UNKNOWN_REGISTER;
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/* Bit 1 is W1C IRQ status. WD1 has no implemented IRQ producer, so it
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* reads zero and clearing it is harmless. IRQ enable and unknown bits
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* fail before polling or changing any state. */
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if (write && (*value > UINT32_MAX ||
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(offset == 0x1c && (*value & ~6UL))))
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return WATCHDOG_BAD_VALUE;
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watchdog_wait(s, now, UINT64_MAX);
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uint32_t *reg = offset == 0x10 ? &s->current :
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offset == 0x14 ? &s->bite : &s->control;
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if (write) {
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*reg = offset == 0x1c ? (uint32_t)*value & 4 : (uint32_t)*value;
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watchdog_wait(s, now, UINT64_MAX);
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} else *value = *reg;
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return WATCHDOG_OK;
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}
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