Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
109 lines
3.8 KiB
C
109 lines
3.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/* See mmu.h. */
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#include "mmu.h"
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/* Index bits per level. A table is one granule of 8-byte entries, so a 16K
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* granule indexes 11 bits per level and a 4K granule 9 -- which is why the 16K
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* and 4K level boundaries do not line up and a shadow is a re-translation
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* rather than a structural rewrite of the guest's tables. */
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static uint32_t index_bits(uint32_t granule_shift)
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{
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return granule_shift - 3;
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}
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/* Lowest VA bit resolved by `level`. Level 3 resolves the granule offset. */
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static uint32_t level_shift(uint32_t granule_shift, uint32_t level)
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{
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return granule_shift + (3 - level) * index_bits(granule_shift);
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}
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uint64_t mmu_level_size(uint32_t granule_shift, uint32_t level)
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{
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return 1UL << level_shift(granule_shift, level);
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}
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uint32_t mmu_index(uint32_t granule_shift, uint32_t level, uint64_t va)
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{
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uint32_t bits = index_bits(granule_shift);
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return (uint32_t)((va >> level_shift(granule_shift, level)) & ((1UL << bits) - 1));
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}
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int mmu_block_allowed(uint32_t granule_shift, uint32_t level)
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{
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/* 4K permits 1GB blocks at L1 and 2MB at L2. 16K and 64K permit blocks only
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* at L2 -- an L1 block would span 64GB and 4TB respectively, which the
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* architecture does not encode. Getting this wrong turns a table descriptor
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* into a huge bogus mapping, so it is checked rather than assumed. */
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if (granule_shift == 12) return level == 1 || level == 2;
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return level == 2;
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}
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int mmu_start_level(uint32_t granule_shift, uint32_t txsz)
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{
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if (txsz > 39 || txsz < 16) return -1;
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uint32_t va_bits = 64 - txsz;
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if (va_bits <= granule_shift) return -1;
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uint32_t bits = index_bits(granule_shift);
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/* The first level whose index reaches the top VA bit. */
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uint32_t levels = (va_bits - granule_shift + bits - 1) / bits;
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if (levels < 1 || levels > 4) return -1;
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return (int)(4 - levels);
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}
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int mmu_walk(const struct mmu_config *cfg, uint64_t va, mmu_read_fn read, void *ctx,
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struct mmu_leaf *out)
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{
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for (unsigned n = 0; n < sizeof(*out); n++) ((uint8_t *)out)[n] = 0;
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if (cfg->granule_shift != 12 && cfg->granule_shift != 14 && cfg->granule_shift != 16)
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return -1;
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int level = mmu_start_level(cfg->granule_shift, cfg->txsz);
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if (level < 0) return -1;
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uint64_t table = cfg->root & PT_OA_MASK;
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uint32_t va_bits = 64 - cfg->txsz;
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/* Only the bits this regime translates; the caller is responsible for
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* having picked the right root for the top bits. */
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uint64_t address = va & (va_bits >= 64 ? ~0UL : ((1UL << va_bits) - 1));
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for (; level <= 3; level++) {
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uint64_t descriptor;
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uint64_t slot = table + 8UL * mmu_index(cfg->granule_shift, (uint32_t)level, address);
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if (read(ctx, slot, &descriptor)) return -1;
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if (!(descriptor & PT_VALID)) {
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out->level = (uint32_t)level;
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out->valid = 0;
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return 0;
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}
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int is_table = (descriptor & PT_TABLE) && level < 3;
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if (is_table) {
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table = descriptor & PT_OA_MASK;
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continue;
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}
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/* A level-3 leaf sets bit 1; a block at levels 0-2 clears it. Anything
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* else is a malformed descriptor, not a mapping. */
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if (level == 3) {
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if (!(descriptor & PT_TABLE)) {
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out->level = 3;
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out->valid = 0;
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return 0;
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}
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} else if (!mmu_block_allowed(cfg->granule_shift, (uint32_t)level)) {
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return -1;
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}
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uint64_t size = mmu_level_size(cfg->granule_shift, (uint32_t)level);
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out->descriptor = descriptor;
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out->base = address & ~(size - 1);
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out->size = size;
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out->pa = (descriptor & PT_OA_MASK & ~(size - 1)) | (address & (size - 1));
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out->level = (uint32_t)level;
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out->valid = 1;
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return 0;
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}
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return -1;
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}
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