Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
199 lines
9.0 KiB
C
199 lines
9.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/* cc -std=c11 -Wall -Wextra -Werror -O1 -g -fsanitize=address,undefined -Icompat
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* tools/test-platform-io.c compat/device.c compat/aic.c compat/watchdog.c
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* compat/clock.c compat/dart.c -o build/test-platform-io; build/test-platform-io */
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#include "device.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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static unsigned checks;
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#define CHECK(x) do { checks++; if (!(x)) { fprintf(stderr,"FAIL %d: %s\n",__LINE__,#x); exit(1); } } while(0)
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static struct device_state state, before;
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static const struct device_model gpio={DEVICE_GPIO_QUIET_V1,0x314838000UL,0x4000,{10,7,0x70,0,0}};
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static const struct device_model aes={DEVICE_AES_NO_KEYS_V1,0x3082dc000UL,0x8000,{0,0x40,0x44,0x48,0}};
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static uint64_t read32(const struct device_model *m, uint64_t offset)
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{
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uint64_t value=UINT64_MAX;
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CHECK(device_model_access_state(m,&state,offset,4,0,&value)==DEVICE_OK);
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return value;
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}
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static void write32(const struct device_model *m, uint64_t offset, uint64_t value)
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{
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CHECK(device_model_access_state(m,&state,offset,4,1,&value)==DEVICE_OK);
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}
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static void refuse(const struct device_model *m, uint64_t offset, unsigned width,
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int write, uint64_t value, enum device_result want)
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{
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before=state;
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uint64_t original=value;
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CHECK(device_model_access_state(m,&state,offset,width,write,&value)==want);
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CHECK(value==original);
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CHECK(!memcmp(&state,&before,sizeof(state)));
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}
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int main(void)
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{
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CHECK(device_models_valid(&gpio,1,0,0));
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CHECK(device_models_valid(&aes,1,0,0));
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CHECK(device_model_start(&gpio,&state,123,24000000)==DEVICE_OK);
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for (unsigned pin=0; pin<10; pin++) {
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CHECK(read32(&gpio,pin*4)==0x4000e);
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write32(&gpio,pin*4,0x40003);
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CHECK(read32(&gpio,pin*4)==0x40003); /* output high */
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write32(&gpio,pin*4,0x40002);
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CHECK(read32(&gpio,pin*4)==0x40002); /* output low */
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write32(&gpio,pin*4,0x4000f);
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CHECK(read32(&gpio,pin*4)==0x4000e); /* input stays externally low */
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}
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for (unsigned group=4; group<7; group++) {
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uint64_t off=0x800+group*0x40;
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CHECK(read32(&gpio,off)==0);
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write32(&gpio,off,UINT32_MAX); /* boot init ACK includes unused bits */
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CHECK(read32(&gpio,off)==0);
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refuse(&gpio,off+4,4,0,0,DEVICE_UNKNOWN_REGISTER);
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}
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refuse(&gpio,0x800,4,1,UINT32_MAX,DEVICE_UNKNOWN_REGISTER);
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refuse(&gpio,40,4,0,0,DEVICE_UNKNOWN_REGISTER);
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refuse(&gpio,0x4000,4,0,0,DEVICE_NOT_FOUND);
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for (unsigned width=1; width<=8; width*=2)
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if (width!=4) refuse(&gpio,0,width,0,0,DEVICE_BAD_WIDTH);
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refuse(&gpio,1,4,0,0,DEVICE_BAD_WIDTH);
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/* A held-low GPIO-function pad can assert only a level-low interrupt.
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* The never-firing modes are admitted; see tools/test-gpio-irq.c. */
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refuse(&gpio,0,4,1,0x40006,DEVICE_BAD_VALUE);
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for (unsigned mode=2; mode<=6; mode++) if (mode!=3) {
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write32(&gpio,0,0x40000 | (mode<<1));
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CHECK(read32(&gpio,0)==(0x40000U | (mode<<1)));
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}
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write32(&gpio,0,0x4000f);
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CHECK(read32(&gpio,0)==0x4000e);
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for (unsigned bit=0; bit<64; bit++)
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if (!((0xe78fefUL>>bit)&1))
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refuse(&gpio,0,4,1,0x4000e | (1UL<<bit),DEVICE_BAD_VALUE);
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refuse(&gpio,0,4,1,0x4002e,DEVICE_BAD_VALUE); /* peripheral mux */
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refuse(&gpio,0,4,1,0x3000e,DEVICE_BAD_VALUE); /* unsupported group */
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write32(&gpio,0,0x240003); /* lock an output high */
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write32(&gpio,0,0x240002); /* data remains writable */
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refuse(&gpio,0,4,1,0x40002,DEVICE_BAD_VALUE); /* no unlocking */
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refuse(&gpio,0,4,1,0x240202,DEVICE_BAD_VALUE);
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CHECK(device_model_start(&gpio,&state,0,24000000)==DEVICE_OK);
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CHECK(read32(&gpio,0)==0x4000e); /* VM reset clears lock and output */
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struct device_model main_gpio=gpio;
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main_gpio.config[0]=216; main_gpio.config[2]=0x7f;
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CHECK(device_model_start(&main_gpio,&state,0,24000000)==DEVICE_OK);
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for (unsigned group=0; group<7; group++) for (unsigned bank=0; bank<7; bank++) {
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write32(&main_gpio,0x800+group*0x40+bank*4,UINT32_MAX);
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CHECK(read32(&main_gpio,0x800+group*0x40+bank*4)==0);
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}
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for (unsigned pin=0; pin<216; pin++) CHECK(read32(&main_gpio,pin*4)==14);
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struct device_model rx=main_gpio;
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rx.kind=DEVICE_GPIO_UART_RX_IDLE_V1; rx.config[3]=0x200aa; rx.config[4]=0;
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CHECK(device_model_start(&rx,&state,0,24000000)==DEVICE_OK);
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write32(&rx,169*4,0x4e); /* stock driver's intermediate input-disabled write */
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CHECK(read32(&rx,169*4)==0x4e);
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write32(&rx,169*4,0x24e);
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CHECK(read32(&rx,169*4)==0x24f); /* disconnected UART receive line is idle high */
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write32(&rx,169*4,0x24f); /* DATA is sampled, not an externally writable input */
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CHECK(read32(&rx,169*4)==0x24f);
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for (unsigned pin=0; pin<216; pin++) if (pin!=169)
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refuse(&rx,pin*4,4,1,0x24e,DEVICE_BAD_VALUE);
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for (unsigned mode=0; mode<7; mode++)
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refuse(&rx,169*4,4,1,0x240 | (mode<<1),DEVICE_BAD_VALUE);
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refuse(&rx,169*4,4,1,0x22e,DEVICE_BAD_VALUE);
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refuse(&rx,169*4,4,1,0x26e,DEVICE_BAD_VALUE);
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write32(&rx,169*4,0x20e); /* disconnecting mux returns to ordinary low GPIO */
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CHECK(read32(&rx,169*4)==0x20e);
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write32(&rx,169*4,0x20024e);
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CHECK(read32(&rx,169*4)==0x20024f);
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refuse(&rx,169*4,4,1,0x20e,DEVICE_BAD_VALUE); /* route is locked */
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CHECK(device_model_start(&rx,&state,0,24000000)==DEVICE_OK);
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CHECK(read32(&rx,169*4)==14);
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rx.config[4]=0x10056; /* UART4's independent idle route */
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write32(&rx,85*4,0x2e);
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CHECK(read32(&rx,85*4)==0x2e);
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write32(&rx,85*4,0x22e);
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CHECK(read32(&rx,85*4)==0x22f);
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write32(&rx,169*4,0x24e);
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CHECK(read32(&rx,169*4)==0x24f);
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CHECK(read32(&rx,85*4)==0x22f);
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for (unsigned i=0; i<5; i++) {
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struct device_model bad=rx;
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if (i==0) bad.config[3]=0x200d9;
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if (i==1) bad.config[3]=0;
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if (i==2) bad.config[4]=0x40056;
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if (i==3) bad.config[4]=0x100aa;
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if (i==4) bad.config[4]=0x10000;
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CHECK(!device_models_valid(&bad,1,0,0));
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}
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struct device_model idle=main_gpio;
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idle.kind=DEVICE_GPIO_IDLE_INPUTS_V1;
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idle.config[3]=0x10056UL | (0x200aaUL<<18) | (0x10066UL<<36);
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idle.config[4]=0;
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CHECK(device_model_start(&idle,&state,0,24000000)==DEVICE_OK);
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const unsigned idle_pins[]={85,169,101}, idle_mux[]={1,2,1};
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for (unsigned i=0; i<3; i++) {
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uint32_t value=14 | (idle_mux[i]<<5);
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write32(&idle,idle_pins[i]*4,value);
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CHECK(read32(&idle,idle_pins[i]*4)==value);
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write32(&idle,idle_pins[i]*4,value|0x200);
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CHECK(read32(&idle,idle_pins[i]*4)==(value|0x201));
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}
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for (unsigned pin=0; pin<216; pin++) if (pin!=85 && pin!=169 && pin!=101)
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refuse(&idle,pin*4,4,1,0x22e,DEVICE_BAD_VALUE);
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for (unsigned mode=0; mode<7; mode++)
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refuse(&idle,101*4,4,1,0x220 | (mode<<1),DEVICE_BAD_VALUE);
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write32(&idle,101*4,0x20e);
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CHECK(read32(&idle,101*4)==0x20e);
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/* Exercise all slots across the two config words, not only slot 0. */
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idle.config[4]=0x10001UL | (0x20002UL<<18) | (0x30003UL<<36);
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CHECK(device_model_start(&idle,&state,0,24000000)==DEVICE_OK);
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for (unsigned pin=0; pin<3; pin++) {
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uint32_t value=0x20e | ((pin+1)<<5);
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write32(&idle,pin*4,value);
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CHECK(read32(&idle,pin*4)==(value|1));
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}
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for (unsigned i=0; i<5; i++) {
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struct device_model bad=idle;
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if (i==0) bad.config[3] |= 1UL<<63;
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if (i==1) bad.config[4] |= 1UL<<54;
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if (i==2) bad.config[4]=0x10066; /* duplicate pin in different word */
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if (i==3) bad.config[3] &= ~0x3ffffUL;
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if (i==4) bad.config[4]=0x100d9; /* pin past end */
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CHECK(!device_models_valid(&bad,1,0,0));
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refuse(&bad,0,4,1,0x22e,DEVICE_BAD_CONFIG);
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}
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CHECK(read32(&aes,0)==15); /* legacy UID/GID and UID0 disable bits */
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for (unsigned i=1; i<4; i++)
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CHECK(read32(&aes,aes.config[i])!=0xa050c030); /* dedicated keys absent */
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for (unsigned i=0; i<4; i++) {
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refuse(&aes,aes.config[i],4,1,0,DEVICE_BAD_VALUE);
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refuse(&aes,aes.config[i],8,0,0,DEVICE_BAD_WIDTH);
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}
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refuse(&aes,4,4,0,0,DEVICE_UNKNOWN_REGISTER);
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refuse(&aes,1,4,0,0,DEVICE_BAD_WIDTH);
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const uint64_t invalid[][2]={{0,0},{0,257},{1,0},{1,8},{2,0},{2,128},{3,1},{4,1}};
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for (unsigned i=0; i<sizeof(invalid)/sizeof(invalid[0]); i++) {
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struct device_model bad=gpio;
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bad.config[invalid[i][0]]=invalid[i][1];
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CHECK(!device_models_valid(&bad,1,0,0));
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refuse(&bad,0,4,0,0,DEVICE_BAD_CONFIG);
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}
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for (unsigned i=0; i<4; i++) {
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struct device_model bad=aes;
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bad.config[i]=aes.config[(i+1)%4];
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CHECK(!device_models_valid(&bad,1,0,0));
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bad=aes; bad.config[i]=0x8000;
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CHECK(!device_models_valid(&bad,1,0,0));
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bad=aes; bad.config[i]++;
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CHECK(!device_models_valid(&bad,1,0,0));
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}
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struct device_model relocated=gpio;
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relocated.base=0x500000000UL;
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CHECK(device_models_valid(&relocated,1,0,0));
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CHECK(device_model_start(&relocated,&state,0,1)==DEVICE_OK);
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CHECK(read32(&relocated,0)==0x4000e);
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printf("PASS: %u GPIO/AES model checks\n",checks);
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return 0;
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}
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