Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
75 lines
3.5 KiB
C
75 lines
3.5 KiB
C
/* SPDX-License-Identifier: MIT */
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#define PMGR_TEST_MISC
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#define main misc_lifecycle_tests
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#include "test-pmgr-venc.c"
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#undef main
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static struct device_state registry[4],snapshot[4];
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static const struct device_model models[]={
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{18,0x300700000,0x11000,{0,0,0,0,0}},
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{18,0x308280000,0x9000,{1,0,0,0,0}},
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{25,0x3003c0000,0x14000,{0x10000,0x1a8,0x1b8,8,DEVICE_PMP_ACTIVE_MASK}},
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{22,0x30827b000,0x1000,{6,0,0,0,0}},
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};
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static enum device_result mmio(unsigned index,unsigned off,unsigned width,int write,uint64_t *v)
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{ return device_models_access_at(models,registry,4,index,0,off,width,write,v); }
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static void init(void)
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{
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memset(registry,0,sizeof(registry));
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for (unsigned i=0;i<4;i++) CHECK(device_model_start(models+i,registry+i,0,24000000)==DEVICE_OK);
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uint64_t v=0x3000;CHECK(mmio(2,0x10c40,8,1,&v)==DEVICE_OK);
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v=1;CHECK(mmio(3,0x800,4,1,&v)==DEVICE_OK);
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}
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int main(int argc,char **argv)
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{
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int result=misc_lifecycle_tests(argc,argv);
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if (argc==2 && !strcmp(argv[1],"--topology")) return result;
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const unsigned levels[3]={0,4,15};
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/* All three independent-domain configurations and transitions preserve
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* non-PMP state, including active AON counter policy and PMP metadata. */
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for (unsigned before=0;before<27;before++) for (unsigned after=0;after<27;after++) {
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init();unsigned pattern=before;
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for (unsigned i=0;i<3;i++) {
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uint64_t v=levels[pattern%3];pattern/=3;
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CHECK(mmio(0,offset(i),4,1,&v)==DEVICE_OK);
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}
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memcpy(snapshot,registry,sizeof(registry));pattern=after;
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for (unsigned i=0;i<3;i++) {
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uint64_t v=levels[pattern%3];pattern/=3;
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CHECK(mmio(0,offset(i),4,1,&v)==DEVICE_OK);
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}
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CHECK(!memcmp(snapshot+1,registry+1,sizeof(registry)-sizeof(registry[0])));
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pattern=after;
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for (unsigned i=0;i<3;i++) {
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uint64_t v=99;CHECK(mmio(0,offset(i),4,0,&v)==DEVICE_OK);
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CHECK((v&255)==17*levels[pattern%3]);pattern/=3;
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}
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}
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init();
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for (unsigned i=0;i<3;i++) {
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for (unsigned width=0;width<=16;width++) if (width!=4) {
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uint64_t v=0;memcpy(snapshot,registry,sizeof(registry));
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CHECK(mmio(0,offset(i),width,1,&v)==DEVICE_BAD_WIDTH);
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CHECK(!memcmp(snapshot,registry,sizeof(registry)));
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}
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for (unsigned delta=1;delta<=4;delta++) {
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uint64_t v=0;memcpy(snapshot,registry,sizeof(registry));
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CHECK(mmio(0,offset(i)+delta,4,1,&v)==(delta==4 ? DEVICE_UNKNOWN_REGISTER : DEVICE_BAD_WIDTH));
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CHECK(!memcmp(snapshot,registry,sizeof(registry)));
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}
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uint64_t v=0;memcpy(snapshot,registry,sizeof(registry));
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CHECK(mmio(1,offset(i),4,1,&v)==DEVICE_UNKNOWN_REGISTER);
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CHECK(!memcmp(snapshot,registry,sizeof(registry)));
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}
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/* Neighbors and CPU/SEP registers must never enter this leaf whitelist. */
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const unsigned fixed[]={0,8,0x10,0x18,0x30,0x38,0x50,0x58,0x60,0x168,0x178,0x198,0x1a8};
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for (unsigned i=0;i<sizeof(fixed)/sizeof(fixed[0]);i++) {
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uint64_t v=0;memcpy(snapshot,registry,sizeof(registry));
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/* SEP_AON requires a complete SEP/DART ownership binding, which this
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* independent-leaf registry deliberately lacks. */
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CHECK(mmio(0,fixed[i],4,1,&v)==(fixed[i]==0x60 ? DEVICE_BAD_CONFIG : DEVICE_BAD_VALUE));
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CHECK(!memcmp(snapshot,registry,sizeof(registry)));
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}
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printf("PMGR independent-leaf registry: %u checks passed\n",checks);
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return result;
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}
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