Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
149 lines
6.1 KiB
C
149 lines
6.1 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "exception.h"
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#include <stdio.h>
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#include <stdlib.h>
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#define CHECK(x) do { checks++; if (!(x)) { fprintf(stderr,"FAIL %d: %s\n",__LINE__,#x); exit(1); } } while(0)
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static unsigned checks;
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int main(void)
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{
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const uint64_t vbar=UINT64_C(0xfffffe000b86c000);
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for(unsigned offset=0;offset<4096;offset++) {
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CHECK(exception_vector_step(UINT64_C(0x32)<<26,vbar+offset,vbar)==
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(offset<0x800 && !(offset&0x7f)));
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}
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CHECK(!exception_vector_step(UINT64_C(0x32)<<26,vbar-128,vbar));
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CHECK(!exception_vector_step(UINT64_C(0x30)<<26,vbar,vbar));
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CHECK(!exception_vector_step(UINT64_C(0x32)<<26,0,0));
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CHECK(!exception_vector_step(UINT64_C(0x32)<<26,vbar+4,vbar+4));
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for(unsigned bits=0;bits<16;bits++) {
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struct exception_step step={0};
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uint64_t original=0xa0400005UL | ((uint64_t)bits<<6);
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uint64_t spsr=original, mdscr=0x8000;
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exception_step_set(&step,0,&spsr,&mdscr);
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CHECK(spsr==original && mdscr==0x8000);
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CHECK(exception_step_fiq(&step,1) && !exception_step_fiq(&step,0));
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for(unsigned n=0;n<3;n++) {
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exception_step_set(&step,1,&spsr,&mdscr);
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CHECK(spsr==((original|(1UL<<21))&~(1UL<<9)) && mdscr==0x8001);
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CHECK(!exception_step_fiq(&step,1));
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}
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exception_step_set(&step,0,&spsr,&mdscr);
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CHECK(spsr==original && mdscr==0x8000);
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CHECK(exception_step_fiq(&step,1));
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spsr^=1UL<<9; original=spsr;
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exception_step_set(&step,0,&spsr,&mdscr);
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CHECK(spsr==original); /* stale saved_d must not leak into a new state */
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exception_step_set(&step,1,&spsr,&mdscr);
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uint64_t saved=spsr;
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CHECK(exception_step_suspend(&step,&saved));
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CHECK(saved==original && !step.active);
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uint64_t handler=0x3c5;
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exception_step_set(&step,0,&handler,&mdscr);
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CHECK(handler==0x3c5 && mdscr==0x8000);
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CHECK(!exception_step_suspend(&step,&saved) && saved==original);
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}
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const uint64_t hcr=0x488000000UL, pc=0xfffffe000c252bfcUL;
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uint64_t out;
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for(unsigned flags=0;flags<256;flags++) for(unsigned mode=8;mode<=9;mode++) {
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uint64_t spsr=((uint64_t)(flags&15)<<28) | ((uint64_t)(flags>>4)<<6) | (1UL<<22) | mode;
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out=0;
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CHECK(exception_kernel_return(0xd69f03e0,hcr,pc,spsr,&out));
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CHECK(out==((spsr&~15UL)|(mode-4)));
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}
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for(unsigned mode=0;mode<32;mode++) if(mode!=8 && mode!=9) {
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out=0xdead;
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CHECK(!exception_kernel_return(0xd69f03e0,hcr,pc,mode,&out));
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CHECK(out==0xdead);
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}
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for(unsigned i=0;i<10;i++) {
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uint64_t h=hcr,p=pc,s=0x204003c8,insn=0xd69f03e0;
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switch(i) {
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case 0: h&=~(1UL<<34);break;
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case 1: h&=~(1UL<<31);break;
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case 2: h&=~(1UL<<27);break;
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case 3: p++;break;
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case 4: p=0x1000;break;
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case 5: s|=1UL<<20;break;
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case 6: s|=1UL<<5;break;
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case 7: s|=1UL<<32;break;
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case 8: insn=0xd69f0bff;break; /* ERETAA */
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case 9: insn=0xd65f03c0;break; /* RET */
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}
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out=0xdead;
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CHECK(!exception_kernel_return(insn,h,p,s,&out));
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CHECK(out==0xdead);
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}
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CHECK(!exception_kernel_return(0xd69f03e0,hcr,pc,8,0));
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const uint64_t user_pc=0x1026f8bf0, user_sp=0x16d85fd58;
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for(unsigned flags=0;flags<256;flags++) {
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uint64_t spsr=((uint64_t)(flags&15)<<28)|((uint64_t)(flags>>4)<<6);
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CHECK(exception_user_return(0xd69f03e0,hcr,user_pc,spsr,&out));
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CHECK(out==spsr);
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}
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for(unsigned bit=0;bit<64;bit++) {
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uint64_t spsr=1UL<<bit;
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int bad=bit<6 || bit==20 || bit>=32;
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out=0xdead;
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CHECK(exception_user_return(0xd69f03e0,hcr,user_pc,spsr,&out)==!bad);
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CHECK(out==(bad ? 0xdead : spsr));
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}
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for(unsigned i=0;i<11;i++) {
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uint64_t h=hcr,p=user_pc,s=0,insn=0xd69f03e0;
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switch(i) {
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case 0:h&=~(1UL<<34);break;
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case 1:h&=~(1UL<<31);break;
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case 2:h&=~(1UL<<27);break;
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case 3:p++;break;
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case 4:p=0;break;
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case 5:p=1UL<<47;break;
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case 6:p=pc;break;
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case 7:s=4;break;
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case 8:s=8;break;
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case 9:insn=0xd69f0bff;break;
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case 10:insn=0xd65f03c0;break;
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}
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out=0xdead;
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CHECK(!exception_user_return(insn,h,p,s,&out) && out==0xdead);
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}
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CHECK(!exception_user_return(0xd69f03e0,hcr,user_pc,0,0));
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for(unsigned mode=0;mode<32;mode++) {
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CHECK(exception_monitor_origin(pc,mode)==(mode==4 || mode==5));
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CHECK(!exception_monitor_origin(user_pc,mode));
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CHECK(!exception_monitor_origin(pc+1,mode));
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}
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CHECK(exception_user_step(0x910003e0,user_pc,user_sp,0xc8000000,0,user_pc+4,user_sp,user_sp));
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/* This shipped entry intentionally accepts an 8-byte-aligned stack and
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* aligns it itself in the next instruction. */
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CHECK(user_sp%16==8);
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for(unsigned i=0;i<10;i++) {
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uint64_t insn=0x910003e0,entry=user_pc,stack=user_sp,esr=0xc8000000;
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uint64_t spsr=0,next=user_pc+4,x0=user_sp,sp=user_sp;
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switch(i) {
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case 0:insn^=1;break;
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case 1:entry++;break;
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case 2:entry=0;break;
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case 3:stack=0;break;
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case 4:esr=0x80000000;break;
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case 5:spsr=4;break;
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case 6:next=user_pc;break;
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case 7:next=pc;break;
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case 8:x0=0;break;
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case 9:sp-=16;break;
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}
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CHECK(!exception_user_step(insn,entry,stack,esr,spsr,next,x0,sp));
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}
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for(unsigned ec=0;ec<64;ec++) for(unsigned fsc=0;fsc<64;fsc++) {
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uint64_t esr=((uint64_t)ec<<26) | (1UL<<25) | fsc;
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CHECK(exception_kernel_page_fault(esr)==
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((ec==0x21 || ec==0x25) && fsc>=4 && fsc<=15));
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for(unsigned vector=0;vector<0x800;vector+=0x80) {
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CHECK(exception_user_sync(vector,0,esr)==(vector==0x400 &&
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(ec==0x15 || ((ec==0x20 || ec==0x24) && fsc>=4 && fsc<=15))));
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CHECK(!exception_user_sync(vector,4,esr));
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CHECK(!exception_user_sync(vector,8,esr));
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CHECK(!exception_user_sync(vector,16,esr));
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}
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}
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printf("PASS: %u kernel/user return, vector and execution-witness checks\n",checks);
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}
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