Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
87 lines
4.3 KiB
C
87 lines
4.3 KiB
C
/* SPDX-License-Identifier: MIT */
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#pragma once
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#include <stdint.h>
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#include "sprr.h"
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/* O(1) permission-variant selection for native page tables
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* (SNAP_NATIVE_TABLES, docs/NATIVE-TABLES-DESIGN-20260929.md section 5).
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*
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* Each address space has two variant trees: w=0 (TPRO pages read-only) and
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* w=1 (TPRO pages writable). Phase 2 adds kernel variants k=0/1 (ROZONE
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* read-only/writable, PPERM bit 8). Every (address space, w, k) has its own
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* hardware ASID, and the monitor keeps every tree exact and invalidates what
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* it changes, so choosing a variant is a TTBR write with no TLB maintenance.
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*
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* w = bit 36 of (el0 ? UPERM : PPERM), k = bit 8 of PPERM.
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*
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* Contract for callers (the EL0/EL1 boundary handler and the SPRR write
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* handlers), all under the monitor's per-CPU state, no locks needed:
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* native_select(n, el0) at every EL0<->EL1 crossing the monitor
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* controls; el0 is the regime about to run.
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* native_set_uperm(n, value, el0) after a UPERM write is accepted;
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* native_set_pperm(n, value, el0) after a PPERM write is accepted.
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* el0 is the regime that resumes: XNU writes
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* UPERM from EL1 too, where PPERM governs.
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* native_install(...) at SWITCH_ROOT (monitor only).
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* Each returns nonzero on success; zero is terminal (do not resume the
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* guest). A CPU with no native address space installed selects nothing and
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* succeeds, so the calls are safe in every build. */
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struct native_cpu {
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uint64_t ttbr0[2][2]; /* [w][k]: variant root | hardware ASID << 48 */
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uint64_t ttbr1[2]; /* [k]: kernel variant root; 0 leaves TTBR1 alone */
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uint64_t uperm,pperm; /* the SPRR values the variant follows */
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uint32_t el0,w,k,installed;
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uint64_t selects,flips,errors;
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};
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_Static_assert(sizeof(struct native_cpu)==104,"native per-CPU selection record");
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static inline unsigned native_variant_w(uint64_t uperm,uint64_t pperm,int el0)
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{return !!((el0 ? uperm : pperm)&SPRR_UPERM_TPRO_WRITE);}
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static inline unsigned native_variant_k(uint64_t pperm)
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{return !!(pperm&UINT64_C(0x100));}
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/* Hardware writes, replaceable for host tests. */
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#ifndef NATIVE_WRITE_TTBR0
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#define NATIVE_WRITE_TTBR0(v) __asm__ volatile("msr ttbr0_el1, %0; isb" :: "r"(v) : "memory")
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#endif
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#ifndef NATIVE_WRITE_TTBR1
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#define NATIVE_WRITE_TTBR1(v) __asm__ volatile("msr ttbr1_el1, %0; isb" :: "r"(v) : "memory")
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#endif
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static inline int native_apply(struct native_cpu *n,int el0)
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{
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n->selects++;
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unsigned w=native_variant_w(n->uperm,n->pperm,el0),k=native_variant_k(n->pperm);
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n->el0=(uint32_t)!!el0;
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if(!n->installed)return 1;
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uint64_t t0=n->ttbr0[w][k];
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if(!t0) {n->errors++;return 0;}
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if(w==n->w && k==n->k)return 1;
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if(k!=n->k && n->ttbr1[k])NATIVE_WRITE_TTBR1(n->ttbr1[k]);
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NATIVE_WRITE_TTBR0(t0);
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n->w=w;n->k=k;n->flips++;return 1;
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}
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static inline int native_select(struct native_cpu *n,int el0)
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{return native_apply(n,el0);}
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static inline int native_set_uperm(struct native_cpu *n,uint64_t uperm,int el0)
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{n->uperm=uperm;return native_apply(n,el0);}
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static inline int native_set_pperm(struct native_cpu *n,uint64_t pperm,int el0)
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{n->pperm=pperm;return native_apply(n,el0);}
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/* SWITCH_ROOT: load an address space's variants for the reset SPRR state
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* (el0: the regime the switch returns to) and return the TTBR0 value the
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* caller's own installation sequence writes (it owns the barriers and any
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* flush); 0 refuses, leaving the CPU uninstalled. The caller also writes
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* ttbr1[k] when that is nonzero. ttbr0 values of unused kernel variants may
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* repeat k=0's until phase 2. Loading is not a flip. */
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static inline uint64_t native_install(struct native_cpu *n,const uint64_t ttbr0[2][2],
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const uint64_t ttbr1[2],uint64_t uperm,uint64_t pperm,int el0)
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{
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for(unsigned w=0;w<2;w++)for(unsigned k=0;k<2;k++)n->ttbr0[w][k]=ttbr0[w][k];
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n->ttbr1[0]=ttbr1 ? ttbr1[0] : 0;n->ttbr1[1]=ttbr1 ? ttbr1[1] : 0;
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n->uperm=uperm;n->pperm=pperm;n->el0=(uint32_t)!!el0;
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n->w=native_variant_w(uperm,pperm,el0);n->k=native_variant_k(pperm);
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uint64_t t0=n->ttbr0[n->w][n->k];
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n->installed=t0!=0;
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if(!t0)n->errors++;
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return t0;
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}
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/* A switch to the kernel root, or a CPU leaving native mode. */
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static inline void native_uninstall(struct native_cpu *n)
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{n->installed=0;n->w=0;n->k=0;}
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