Acelogic
1510d8c6ce
An EL2 monitor/hypervisor and toolchain that boots macOS 27 on the ASUS A16 (Snapdragon X2 Elite), with an Adreno Metal plug-in and IOGPU kext, and air2ir3, an AIR to Mesa ir3 shader compiler. MIT, with GPL-2.0 components listed in LICENSE and THIRD_PARTY_NOTICES.md. No Apple, Qualcomm, ASUS or Microsoft binaries are included.
135 lines
6.4 KiB
C
135 lines
6.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/* Replay the stock cluster-enable RMW/poll and independent gating policies. */
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "device.h"
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static unsigned checks;
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#define CHECK(x) do { checks++; if (!(x)) { \
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fprintf(stderr,"line %u: %s\n",__LINE__,#x); exit(1); } } while (0)
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static struct device_state states[2], saved, other;
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static const struct device_model models[]={
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{DEVICE_PMGR_CPU_CLUSTER_ACTIVE_V1,0x300780000,0x1000,{0,0,0,0,0}},
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{DEVICE_PMGR_SOC_GATE_POLICY_V1,0x300724000,0x1000,{0,0,0,0,0}},
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};
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static const unsigned gates[]={0,0x40,0x60,0x68};
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static enum device_result access_word(unsigned model,unsigned off,unsigned width,
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int write,uint64_t *v)
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{
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return device_model_access_state(&models[model],&states[model],off,width,write,v);
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}
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int main(void)
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{
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CHECK(device_models_valid(models,2,0,0));
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for (unsigned m=0;m<2;m++) {
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CHECK(device_model_start(&models[m],&states[m],0,24000000)==DEVICE_OK);
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/* Exhaust the page: unknown offsets must neither return data nor
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* corrupt the neighboring policy/transport state. */
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unsigned admitted=0;
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for (unsigned off=0;off<0x1000;off+=4) {
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int index=-1;
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if (!m && off<=4) index=(int)(off/4);
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if (m) for (unsigned i=0;i<4;i++) if (off==gates[i]) index=(int)i;
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uint64_t v=0x13579bdf;saved=states[m];
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if (index<0) {
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for (int write=0;write<=1;write++) {
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CHECK(access_word(m,off,4,write,&v)==DEVICE_UNKNOWN_REGISTER);
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CHECK(v==0x13579bdf && !memcmp(&states[m],&saved,sizeof(saved)));
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}
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continue;
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}
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admitted++;
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CHECK(access_word(m,off,4,0,&v)==DEVICE_OK);
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CHECK(v==(m ? 0 : 15));
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CHECK(!memcmp(&states[m],&saved,sizeof(saved)));
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/* AppleT8140PMGR preserves the upper bits, requests active in
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* bits 0..3, then polls bit 4 for zero. */
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if (!m) {
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v=(v&~15UL)|15;
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CHECK(access_word(m,off,4,1,&v)==DEVICE_OK);
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v=UINT64_MAX;
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CHECK(access_word(m,off,4,0,&v)==DEVICE_OK);
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CHECK((v&0x10)==0 && (v&15)==15);
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CHECK(!memcmp(&states[m],&saved,sizeof(saved)));
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for (unsigned requested=0;requested<16;requested++) {
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v=requested;
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CHECK(access_word(m,off,4,1,&v)==
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(requested==15 ? DEVICE_OK : DEVICE_BAD_VALUE));
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CHECK(v==requested && !memcmp(&states[m],&saved,sizeof(saved)));
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}
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} else {
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/* restoreHW sets bit 31; enableCPMPowerDomainGating can
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* clear it. No request changes another word or instance. */
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for (unsigned enabled=0;enabled<4;enabled++) {
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v=UINT64_MAX;
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CHECK(access_word(m,off,4,0,&v)==DEVICE_OK);
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v=(v&0x7fffffff)|((uint64_t)(enabled&1)<<31);
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CHECK(access_word(m,off,4,1,&v)==DEVICE_OK);
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saved.pmgr_soc_gate[index]=(uint32_t)v;
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CHECK(!memcmp(&states[m],&saved,sizeof(saved)));
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v=UINT64_MAX;
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CHECK(access_word(m,off,4,0,&v)==DEVICE_OK);
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CHECK(v==((uint64_t)(enabled&1)<<31));
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}
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}
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for (unsigned bit=0;bit<64;bit++) {
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v=(m ? 0x80000000UL : 15UL)^(1UL<<bit);
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uint64_t input=v;saved=states[m];
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int valid=m && bit==31;
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CHECK(access_word(m,off,4,1,&v)==(valid ? DEVICE_OK : DEVICE_BAD_VALUE));
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if (valid) saved.pmgr_soc_gate[index]=0;
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CHECK(v==input && !memcmp(&states[m],&saved,sizeof(saved)));
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}
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for (unsigned width=1;width<=16;width*=2) {
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if (width==4) continue;
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for (int write=0;write<=1;write++) {
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v=15;saved=states[m];
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CHECK(access_word(m,off,width,write,&v)==DEVICE_BAD_WIDTH);
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CHECK(v==15 && !memcmp(&states[m],&saved,sizeof(saved)));
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}
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}
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for (unsigned delta=1;delta<=3;delta++) for (int write=0;write<=1;write++) {
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v=15;saved=states[m];
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CHECK(access_word(m,off+delta,4,write,&v)==DEVICE_BAD_WIDTH);
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CHECK(v==15 && !memcmp(&states[m],&saved,sizeof(saved)));
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}
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}
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CHECK(admitted==(m ? 4 : 2));
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uint64_t v=15;saved=states[m];
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CHECK(access_word(m,0x1000,4,0,&v)==DEVICE_NOT_FOUND);
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CHECK(device_model_access_state(&models[m],0,0,4,0,&v)==DEVICE_BAD_CONFIG);
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CHECK(device_model_access_state(&models[m],&states[m],0,4,0,0)==DEVICE_BAD_CONFIG);
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for (unsigned i=0;i<5;i++) {
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/* config[0] selects a cluster variant (up to the AVE cluster);
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* one past the last variant is the unknown value here. */
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struct device_model bad=models[m];
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bad.config[i]=models[m].kind==DEVICE_PMGR_CPU_CLUSTER_ACTIVE_V1 && !i ?
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DEVICE_PMGR_AVE_CLUSTER_V1+1 : 1;
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CHECK(!device_models_valid(&bad,1,0,0));
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CHECK(device_model_start(&bad,&states[m],0,24000000)==DEVICE_BAD_CONFIG);
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CHECK(device_model_access_state(&bad,&states[m],0,4,1,&v)==DEVICE_BAD_CONFIG);
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CHECK(!memcmp(&states[m],&saved,sizeof(saved)));
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}
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struct device_model bad=models[m];bad.span=0x4000;
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CHECK(!device_models_valid(&bad,1,0,0));
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}
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/* A new VM starts with its own zero policy; reset touches only owned
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* words, preserving the surrounding union and legacy transport state. */
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memset(&other,0,sizeof(other));
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CHECK(device_model_start(&models[1],&other,0,24000000)==DEVICE_OK);
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for (unsigned i=0;i<4;i++) {
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uint64_t v=0x80000000;
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CHECK(access_word(1,gates[i],4,1,&v)==DEVICE_OK);
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CHECK(other.pmgr_soc_gate[i]==0);
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}
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states[1].dram_policy=0xfeed;states[1].ptd_ack=3;
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states[1].pmgr_policy[4]=0xfeedbeef;saved=states[1];
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for (unsigned i=0;i<4;i++) saved.pmgr_soc_gate[i]=0;
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CHECK(device_model_start(&models[1],&states[1],123,24000000)==DEVICE_OK);
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CHECK(!memcmp(&states[1],&saved,sizeof(saved)));
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printf("PMGR CPU cluster and SOC gating: %u checks passed\n",checks);
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return 0;
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}
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