compat: add the kext's IO-coherent maintenance-skip rules
compat/adreno-coherent-skip.h (only with -DADRENO_COHERENT_SKIP_MAINT=1) decides, per map and per kernel command, how an AdrenoX2 maintains CPU caches once the monitor's ADRENO_GUEST_COHERENT QUERY answers ON: - PLAIN: today's ADRENO_GUEST_CACHE when there is no ON answer (older monitor, failed self-test, boot-arg absent, or a forced ON the kext was not told to accept) or the backing's declared cache mode is not write-back; - CALL: ADRENO_GUEST_CACHE with ADRENO_CACHE_COHERENT, where the monitor maintains only the frames the CPU does not map write-back; a whole-map pass that needed none records a verdict at the current CPU attribute epoch; - SKIP: no call, only while that verdict's epoch is still current. tools/test-adreno-coherent-kext.c drives these rules the way AdrenoMemoryMap's cacheSubmission and cacheRange do against a model of the CPU data cache, per-frame attributes and the monitor's answers, including epoch changes, forced answers and malformed replies.
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@@ -0,0 +1,64 @@
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/* SPDX-License-Identifier: MIT */
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/* compat/adreno-coherent-skip.h - IO-coherent CB0 leaves (-DADRENO_COHERENT_SKIP_MAINT=1, AdrenoMemoryMap.cpp and
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* tools/test-adreno-coherent-kext.c): when the kext may leave out a map's CPU cache maintenance.
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*
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* Why: with IO-coherent CB0 leaves (the monitor's boot self-test proved that GPU accesses snoop the CPU's caches,
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* compat/adreno-guest.h ADRENO_GUEST_COHERENT), memory the CPU maps write-back needs no DC CIVAC before a GPU read
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* and no DC IVAC after a GPU write. The CPU's attribute is the monitor's to know (it mediates every SPTM SH/AttrIndx
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* change), so a map is skipped only after the monitor found every frame of it write-back, and only at the attribute
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* epoch it found that at:
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* PLAIN today's ADRENO_GUEST_CACHE: no ON answer (self-test failed, older monitor, boot-arg absent, or a
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* debug monitor's forced ON without the kext's own adreno_coherent_force=1), or a
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* backing whose declared cache mode is not write-back (an IOSurface in inhibit, write-through,
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* write-combine or another mode: kept even after AdrenoDisplay converts a framebuffer to write-back);
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* CALL ADRENO_GUEST_CACHE with ADRENO_CACHE_COHERENT: the monitor maintains only the frames the CPU does not
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* map write-back and says how many bytes that was (x2); a whole-map pass with 0 makes the verdict;
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* SKIP the verdict holds at the current epoch: no call, validation only.
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* Header-only so the host model runs exactly these rules. */
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#pragma once
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#include <stdint.h>
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#include "adreno-guest.h"
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#ifndef ADRENO_COHERENT_SKIP_MAINT
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#define ADRENO_COHERENT_SKIP_MAINT 0
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#endif
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#if ADRENO_COHERENT_SKIP_MAINT
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/* The monitor's answer as the kext last read it (AdrenoMemoryMap::coherentRefresh, start of every kernel command,
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* under the submission lock). on: QUERY answered ABI 1 and state ON with a nonzero epoch, and, when the detail says
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* the ON was forced (ADRENO_COHERENT_DETAIL_FORCED: no self-test ran), the kext was told to accept that. */
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struct adreno_coherent_gate { uint64_t asked, on, epoch, answer, forced; };
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enum { ADRENO_COHERENT_PLAIN = 0, ADRENO_COHERENT_CALL = 1, ADRENO_COHERENT_SKIP = 2 };
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static inline void adreno_coherent_gate_reply(struct adreno_coherent_gate *g, uint64_t x0, uint64_t x1, uint64_t x2,
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int accept_forced)
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{
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g->asked = 1;
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g->answer = x0 ? 0 : x1;
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g->forced = !x0 && ((x1 >> 16) & ADRENO_COHERENT_DETAIL_FORCED);
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g->on = !x0 && (x1 & 0xff) == ADRENO_COHERENT_ABI && ((x1 >> 8) & 0xff) == ADRENO_COHERENT_STATE_ON && x2 &&
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(!g->forced || accept_forced);
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g->epoch = g->on ? x2 : 0;
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}
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/* declared_wb: the backing is not an IOSurface, or an IOSurface whose getCacheMode() is default or copyback.
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* verdict: the epoch at which the monitor found every frame write-back, 0 for none. */
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static inline unsigned adreno_coherent_choose(const struct adreno_coherent_gate *g, int declared_wb, uint64_t verdict)
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{
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if (!g->on || !declared_wb) return ADRENO_COHERENT_PLAIN;
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return verdict && verdict == g->epoch ? ADRENO_COHERENT_SKIP : ADRENO_COHERENT_CALL;
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}
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/* x3 of a maintenance call, and whether its reply is a success: a coherent call may report up to `bytes` still
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* maintained in x2; a plain one reports 0 there. */
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static inline uint64_t adreno_coherent_direction(unsigned how, unsigned direction)
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{
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return how == ADRENO_COHERENT_CALL ? (uint64_t)direction | ADRENO_CACHE_COHERENT : direction;
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}
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static inline int adreno_coherent_reply_ok(unsigned how, uint64_t bytes, uint64_t x0, uint64_t x1, uint64_t x2)
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{
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return !x0 && x1 == bytes && (how == ADRENO_COHERENT_CALL ? x2 <= bytes : !x2);
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}
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/* After a whole-map pass of coherent calls: its verdict (a range pass never makes one). */
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static inline uint64_t adreno_coherent_verdict(const struct adreno_coherent_gate *g, int result, uint64_t maintained)
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{
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return !result && !maintained ? g->epoch : 0;
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}
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#endif
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@@ -0,0 +1,279 @@
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/* SPDX-License-Identifier: MIT */
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/* The kext's half of IO-coherent CB0 leaves (ADRENO_COHERENT_SKIP_MAINT): compat/adreno-coherent-skip.h's rules, driven the way AdrenoMemoryMap's cacheSubmission and cacheRange drive
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* them, against a model of the rest of the machine:
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* - the CPU's data cache (64-byte lines: present, dirty) over DRAM, and each 16 KiB frame's CPU attribute (WB or
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* NC). An NC store goes to DRAM and leaves any line alone; an NC frame can hold a stale clean line (speculation
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* through a write-back alias), which a snooping GPU read would return;
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* - the monitor: QUERY (state, epoch), plain ADRENO_GUEST_CACHE (DC CIVAC / DC IVAC on every line) and the coherent
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* variant (refused unless ON; only non-WB frames maintained; x2 = their bytes), an SPTM attribute change (cleans
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* the frame, moves the epoch);
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* - the GPU: copies one buffer into another; with coherent leaves on a coherent machine its reads snoop the CPU's
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* lines and its writes drop them, otherwise it sees DRAM only.
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* Every buffer class runs several command buffers (CPU writes the source, the kext maintains, the GPU copies, the kext
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* maintains, the CPU reads the destination), and every byte read back must be what the CPU wrote. The class rules
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* (PLAIN / CALL / SKIP per pass) are checked too.
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*
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* clang -std=gnu11 -Icompat -O1 -g -fsanitize=address,undefined -Wall -Wextra -Werror \
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* -DADRENO_COHERENT_SKIP_MAINT=1 tools/test-adreno-coherent-kext.c -o build/test-adreno-coherent-kext \
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* && build/test-adreno-coherent-kext
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* Run from the tree root. No hardware client. */
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "adreno-coherent-skip.h"
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#if !ADRENO_COHERENT_SKIP_MAINT
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#error "build with -DADRENO_COHERENT_SKIP_MAINT=1"
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#endif
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static unsigned checks, failures;
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#define CHECK(x) do { checks++; if (!(x)) { failures++; printf("FAIL %d: %s\n", __LINE__, #x); } } while (0)
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/* --- the machine ---------------------------------------------------------------------------------------------- */
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#define FRAMES 8
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#define FRAME 0x4000u
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#define LINES (FRAMES * FRAME / 64)
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static uint32_t dram[FRAMES * FRAME / 4], cache[FRAMES * FRAME / 4];
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static uint8_t present[LINES], dirty[LINES], nc[FRAMES];
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static struct {
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int coherent_hw; /* the interconnect snoops coherent-leaf GPU accesses */
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unsigned state; /* ADRENO_COHERENT_STATE_* */
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int old_monitor; /* QUERY refused: a monitor without SNAP_ADRENO_COHERENT */
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uint64_t epoch, plain_calls, coherent_calls, maintained, refused;
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} mon;
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static void cpu_line_fill(unsigned line)
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{
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if (!present[line]) { memcpy(&cache[line * 16], &dram[line * 16], 64); present[line] = 1; dirty[line] = 0; }
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}
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static void cpu_write(uint32_t off, uint32_t v)
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{
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if (nc[off / FRAME]) { dram[off / 4] = v; return; } /* NC: straight to DRAM, lines left alone */
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cpu_line_fill(off / 64);
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cache[off / 4] = v;
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dirty[off / 64] = 1;
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}
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static uint32_t cpu_read(uint32_t off)
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{
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if (nc[off / FRAME]) return dram[off / 4];
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cpu_line_fill(off / 64);
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return cache[off / 4];
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}
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static void dc_civac(unsigned line) { if (present[line] && dirty[line]) memcpy(&dram[line * 16], &cache[line * 16], 64); present[line] = dirty[line] = 0; }
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static void dc_ivac(unsigned line) { present[line] = dirty[line] = 0; }
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/* A speculative fill through a write-back alias: a clean line with what DRAM holds now. */
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static void speculate(uint32_t off) { unsigned line = off / 64; if (!present[line]) { memcpy(&cache[line * 16], &dram[line * 16], 64); present[line] = 1; } }
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static int gpu_coherent(void) { return mon.state == ADRENO_COHERENT_STATE_ON && mon.coherent_hw; }
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static uint32_t gpu_read(uint32_t off)
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{
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unsigned line = off / 64;
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if (gpu_coherent() && present[line]) return cache[off / 4]; /* snooped: the line answers, stale or not */
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return dram[off / 4];
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}
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static void gpu_write(uint32_t off, uint32_t v)
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{
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unsigned line = off / 64;
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if (gpu_coherent() && present[line]) { if (dirty[line]) memcpy(&dram[line * 16], &cache[line * 16], 64); present[line] = dirty[line] = 0; }
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dram[off / 4] = v;
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}
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/* An SPTM SH/AttrIndx change of one frame: cleaned to PoC before and after (sptm_attr_clean), the epoch moves. */
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static void attr_change(unsigned frame, int to_nc)
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{
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for (unsigned l = frame * FRAME / 64; l < (frame + 1) * FRAME / 64; l++) dc_civac(l);
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nc[frame] = (uint8_t)to_nc;
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mon.epoch++;
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}
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/* --- the monitor's calls ---------------------------------------------------------------------------------------- */
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static void query(uint64_t r[4])
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{
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if (mon.old_monitor) { r[0] = (uint64_t)-60; r[1] = r[2] = r[3] = 0; return; } /* the fence handler refuses */
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r[0] = 0; r[1] = ADRENO_COHERENT_ABI | (uint64_t)mon.state << 8; r[2] = mon.epoch; r[3] = 14;
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}
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static void cache_call(uint32_t off, uint32_t bytes, uint64_t x3, uint64_t r[4])
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{
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unsigned direction = (unsigned)(x3 & ~(uint64_t)ADRENO_CACHE_COHERENT);
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int coherent = !!(x3 & ADRENO_CACHE_COHERENT);
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if (coherent && mon.state != ADRENO_COHERENT_STATE_ON) { mon.refused++; r[0] = (uint64_t)-60; r[1] = r[2] = 0; return; }
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uint64_t maintained = 0;
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for (uint32_t at = off; at < off + bytes; at += 64) {
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if (coherent && !nc[at / FRAME]) continue; /* the CPU's write-back frame: left alone */
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if (direction == ADRENO_CACHE_TO_DEVICE) dc_civac(at / 64); else dc_ivac(at / 64);
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maintained += 64;
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}
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if (coherent) { mon.coherent_calls++; mon.maintained += maintained; } else mon.plain_calls++;
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r[0] = 0; r[1] = bytes; r[2] = coherent ? maintained : 0; r[3] = 0;
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}
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/* --- the kext, as AdrenoMemoryMap drives the rules -------------------------------------------------------------- */
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struct map { uint32_t off, bytes; int declared_wb; uint64_t verdict, maintained; unsigned how; };
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static struct adreno_coherent_gate gate;
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static int wanted; /* the boot-arg adreno_coherent=1 */
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static void refresh(void) /* coherentRefresh: every kernel command */
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{
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static int off_for_boot;
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if (!wanted || off_for_boot) return;
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uint64_t r[4];
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query(r);
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adreno_coherent_gate_reply(&gate, r[0], r[1], r[2], 0);
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if (!gate.on) off_for_boot = 1;
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}
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static int maintain(struct map *m, uint32_t off, uint32_t bytes, unsigned direction) /* maintainCache */
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{
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uint64_t r[4];
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cache_call(off, bytes, adreno_coherent_direction(m->how, direction), r);
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if (!adreno_coherent_reply_ok(m->how, bytes, r[0], r[1], r[2])) return -1;
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if (m->how == ADRENO_COHERENT_CALL) m->maintained += r[2];
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return 0;
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}
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static unsigned passes[3];
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static int sync_map(struct map *m, unsigned direction) /* cacheSubmission */
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{
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m->how = direction ? adreno_coherent_choose(&gate, m->declared_wb, m->verdict) : ADRENO_COHERENT_PLAIN;
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m->maintained = 0;
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passes[m->how]++;
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if (m->how == ADRENO_COHERENT_SKIP) direction = 0;
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int result = 0;
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for (uint32_t at = 0; direction && at < m->bytes && !result; at += 0x4000) /* 16 KiB chunks */
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result = maintain(m, m->off + at, m->bytes - at < 0x4000 ? m->bytes - at : 0x4000, direction);
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if (m->how == ADRENO_COHERENT_CALL) m->verdict = adreno_coherent_verdict(&gate, result, m->maintained);
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m->how = ADRENO_COHERENT_PLAIN;
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return result;
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}
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static void repin(struct map *m) { m->verdict = 0; } /* pinBacking/unpinBacking */
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/* One command buffer: the CPU writes `src` (with a stale clean line first in NC frames), TO_DEVICE on both maps, the
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* GPU copies src -> dst, FROM_DEVICE on dst, the CPU reads dst. Returns the words that differ from what was written,
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* or -1 when a maintenance call failed. */
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static int command(struct map *src, struct map *dst, uint32_t seed)
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{
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refresh();
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for (uint32_t i = 0; i < src->bytes; i += 4) {
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if (nc[(src->off + i) / FRAME]) speculate(src->off + i);
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cpu_write(src->off + i, seed + i);
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}
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for (uint32_t i = 0; i < dst->bytes; i += 64) (void)cpu_read(dst->off + i); /* the CPU had looked at the target */
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if (sync_map(src, ADRENO_CACHE_TO_DEVICE) || sync_map(dst, ADRENO_CACHE_TO_DEVICE)) return -1;
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for (uint32_t i = 0; i < src->bytes; i += 4) gpu_write(dst->off + i, gpu_read(src->off + i));
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if (sync_map(dst, ADRENO_CACHE_FROM_DEVICE)) return -1;
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int bad = 0;
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for (uint32_t i = 0; i < src->bytes; i += 4) bad += cpu_read(dst->off + i) != seed + i;
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return bad;
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}
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static void reset(unsigned state, int coherent_hw)
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{
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memset(dram, 0, sizeof dram); memset(cache, 0, sizeof cache); memset(present, 0, sizeof present);
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memset(dirty, 0, sizeof dirty); memset(nc, 0, sizeof nc); memset(&mon, 0, sizeof mon); memset(&gate, 0, sizeof gate);
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memset(passes, 0, sizeof passes);
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mon.state = state; mon.coherent_hw = coherent_hw; mon.epoch = 7; wanted = 1;
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}
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#define M(frame, wb) {(frame) * FRAME, 2 * FRAME, (wb), 0, 0, 0}
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/* A Metal buffer (IOGPU memory, the CPU's write-back): the first pass verifies, later ones skip. */
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static void test_writeback_buffer(void)
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{
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reset(ADRENO_COHERENT_STATE_ON, 1);
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struct map a = M(0, 1), b = M(2, 1);
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for (unsigned n = 0; n < 4; n++) CHECK(command(&a, &b, 0x1000 * n) == 0);
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/* The first command verifies the source (TO_DEVICE) and the target (TO_DEVICE); its FROM_DEVICE already skips. */
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CHECK(a.verdict == 7 && b.verdict == 7 && passes[ADRENO_COHERENT_CALL] == 2 && passes[ADRENO_COHERENT_SKIP] == 10);
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CHECK(mon.maintained == 0 && mon.plain_calls == 0);
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printf("KEXT write-back: %u calls, %u skips, 0 bytes maintained\n", passes[ADRENO_COHERENT_CALL],
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passes[ADRENO_COHERENT_SKIP]);
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}
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/* A buffer the CPU maps write-combined (NC frames): every pass asks, the monitor maintains, never a verdict. */
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static void test_wc_buffer(void)
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{
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reset(ADRENO_COHERENT_STATE_ON, 1);
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nc[0] = nc[1] = 1;
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struct map a = M(0, 1), b = M(2, 1);
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for (unsigned n = 0; n < 4; n++) CHECK(command(&a, &b, 0x2000 * n) == 0);
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CHECK(a.verdict == 0 && passes[ADRENO_COHERENT_SKIP] == 7 && passes[ADRENO_COHERENT_CALL] == 5 &&
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mon.maintained == 4 * 2 * FRAME);
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}
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/* An IOSurface declared write-combine keeps today's maintenance, even when its frames are write-back now. */
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static void test_wc_surface(void)
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{
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reset(ADRENO_COHERENT_STATE_ON, 1);
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struct map a = M(0, 0), b = M(2, 1);
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for (unsigned n = 0; n < 3; n++) CHECK(command(&a, &b, 0x3000 * n) == 0);
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CHECK(a.verdict == 0 && mon.plain_calls == 3 * 2 && passes[ADRENO_COHERENT_PLAIN] == 3);
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}
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/* Write-back verified, then the frame turns NC (the monitor cleans it, the epoch moves): the next pass asks
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* again and the NC frame is maintained; a re-pin forgets the verdict too. */
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static void test_epoch_and_repin(void)
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{
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reset(ADRENO_COHERENT_STATE_ON, 1);
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struct map a = M(0, 1), b = M(2, 1);
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CHECK(command(&a, &b, 0x4000) == 0 && command(&a, &b, 0x5000) == 0 && a.verdict == 7);
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attr_change(0, 1);
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CHECK(command(&a, &b, 0x6000) == 0 && a.verdict == 0 && b.verdict == 8 && mon.maintained == FRAME);
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CHECK(command(&a, &b, 0x7000) == 0 && a.verdict == 0);
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attr_change(0, 0);
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CHECK(command(&a, &b, 0x8000) == 0 && a.verdict == 9);
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repin(&a);
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const unsigned calls = passes[ADRENO_COHERENT_CALL];
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CHECK(command(&a, &b, 0x9000) == 0 && passes[ADRENO_COHERENT_CALL] == calls + 1 && a.verdict == 9);
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}
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/* No ON answer means today's maintenance; nothing is asked of a monitor that said OFF or refused. */
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static void test_off(void)
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{
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static const struct { unsigned state; int old, wanted; const char *what; } cases[] = {
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{ADRENO_COHERENT_STATE_FAILED, 0, 1, "self-test failed"}, {ADRENO_COHERENT_STATE_INCONCLUSIVE, 0, 1, "no power"},
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{ADRENO_COHERENT_STATE_ON, 1, 1, "older monitor"}, {ADRENO_COHERENT_STATE_ON, 0, 0, "boot-arg absent"}};
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for (unsigned i = 0; i < sizeof cases / sizeof cases[0]; i++) {
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reset(cases[i].state, 0); /* a machine that is not coherent */
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mon.old_monitor = cases[i].old;
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wanted = cases[i].wanted;
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struct map a = M(0, 1), b = M(2, 1);
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for (unsigned n = 0; n < 3; n++) CHECK(command(&a, &b, 0x100 * n + i) == 0);
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CHECK(!gate.on && mon.coherent_calls == 0 && mon.refused == 0 && passes[ADRENO_COHERENT_SKIP] == 0);
|
||||
}
|
||||
}
|
||||
/* A gate that is not ON never sends the coherent flag; the monitor would refuse it anyway. */
|
||||
static void test_rules(void)
|
||||
{
|
||||
struct adreno_coherent_gate g;
|
||||
memset(&g, 0, sizeof g);
|
||||
adreno_coherent_gate_reply(&g, 0, ADRENO_COHERENT_ABI | ADRENO_COHERENT_STATE_ON << 8, 0, 0);
|
||||
CHECK(!g.on); /* epoch 0 is not an answer */
|
||||
adreno_coherent_gate_reply(&g, 0, 2 | ADRENO_COHERENT_STATE_ON << 8, 5, 0);
|
||||
CHECK(!g.on); /* another ABI */
|
||||
/* A debug monitor's forced ON counts only with the kext's own boot-arg; the flag alone never turns a state ON,
|
||||
* and the self-test's own flags (0xc000: today's leaves already snooped) are not the forced one. */
|
||||
const uint64_t forced = (uint64_t)ADRENO_COHERENT_DETAIL_FORCED << 16;
|
||||
adreno_coherent_gate_reply(&g, 0, ADRENO_COHERENT_ABI | ADRENO_COHERENT_STATE_ON << 8 | forced, 5, 0);
|
||||
CHECK(!g.on && g.forced && !g.epoch);
|
||||
adreno_coherent_gate_reply(&g, 0, ADRENO_COHERENT_ABI | ADRENO_COHERENT_STATE_ON << 8 | forced, 5, 1);
|
||||
CHECK(g.on && g.forced && g.epoch == 5);
|
||||
adreno_coherent_gate_reply(&g, 0, ADRENO_COHERENT_ABI | ADRENO_COHERENT_STATE_INCONCLUSIVE << 8 | forced, 5, 1);
|
||||
CHECK(!g.on);
|
||||
adreno_coherent_gate_reply(&g, 0, ADRENO_COHERENT_ABI | ADRENO_COHERENT_STATE_ON << 8 | 0xc000ull << 16, 5, 0);
|
||||
CHECK(g.on && !g.forced);
|
||||
adreno_coherent_gate_reply(&g, 0, ADRENO_COHERENT_ABI | ADRENO_COHERENT_STATE_ON << 8, 5, 1);
|
||||
CHECK(g.on && !g.forced); /* the boot-arg changes nothing for a proved ON */
|
||||
adreno_coherent_gate_reply(&g, 0, ADRENO_COHERENT_ABI | ADRENO_COHERENT_STATE_ON << 8, 5, 0);
|
||||
CHECK(g.on && g.epoch == 5 && adreno_coherent_choose(&g, 1, 0) == ADRENO_COHERENT_CALL &&
|
||||
adreno_coherent_choose(&g, 1, 5) == ADRENO_COHERENT_SKIP && adreno_coherent_choose(&g, 1, 4) == ADRENO_COHERENT_CALL &&
|
||||
adreno_coherent_choose(&g, 0, 5) == ADRENO_COHERENT_PLAIN);
|
||||
CHECK(adreno_coherent_direction(ADRENO_COHERENT_CALL, 1) == (1 | ADRENO_CACHE_COHERENT) &&
|
||||
adreno_coherent_direction(ADRENO_COHERENT_PLAIN, 2) == 2);
|
||||
CHECK(adreno_coherent_reply_ok(ADRENO_COHERENT_CALL, 64, 0, 64, 64) && !adreno_coherent_reply_ok(ADRENO_COHERENT_CALL, 64, 0, 64, 65) &&
|
||||
!adreno_coherent_reply_ok(ADRENO_COHERENT_PLAIN, 64, 0, 64, 64) && !adreno_coherent_reply_ok(ADRENO_COHERENT_CALL, 64, 1, 64, 0));
|
||||
CHECK(adreno_coherent_verdict(&g, 0, 0) == 5 && !adreno_coherent_verdict(&g, 0, 64) && !adreno_coherent_verdict(&g, -1, 0));
|
||||
adreno_coherent_gate_reply(&g, (uint64_t)-60, 0, 0, 1);
|
||||
CHECK(!g.on && !g.epoch && adreno_coherent_choose(&g, 1, 5) == ADRENO_COHERENT_PLAIN);
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
test_rules();
|
||||
test_writeback_buffer();
|
||||
test_wc_buffer();
|
||||
test_wc_surface();
|
||||
test_epoch_and_repin();
|
||||
test_off();
|
||||
if (failures) { printf("FAIL: %u of %u kext coherent checks\n", failures, checks); return 1; }
|
||||
printf("PASS: %u kext coherent checks\n", checks);
|
||||
return 0;
|
||||
}
|
||||
Reference in new issue
Block a user