darceye
7f5f1aaa88
- passive probes (new `static passive = true` device metadata): a pure listener never drives an input and claims no pad, so it may clamp onto ANY GPIO - including pads other devices own (an LED, an I2C pair, a MAX7219 bus) and other analyzers. The runtime's pin-conflict check and the wired-AND arbitration skip passive pads; the panel's usedPins ignores them, so other devices' pickers never show them as "in use"; the analyzer's channel grid never disables a GPIO (pads owned elsewhere get a dashed "shared" hint). Replaces the analyzer's sharedBus flag. - trigger on any GPIO: trigCh (channel index) becomes trigPin (GPIO number) - the trigger pad gets its own subscription and need not be an analysed channel (off-channel triggers land in no lane, channel levels still snapshot at capture start). The window dropdown lists every valid GPIO. Tooltip documents the gpio_state visibility caveat: a trigger fires only when the FIRMWARE drives the pad - pure-input pads (driven by our button devices) never toggle the output registers. - window cap lifted 1 s -> 1 h of guest time (was a conservative guard; dense signals still freeze earlier at the 20 000-edge buffer with the buffer-full note - the natural limit, since Saleae streams into host RAM while we capture into a fixed buffer). - tests: runtime-level passive sharing (probe onto an LED pad + I2C pair + second probe, zero conflicts), off-channel trigger, 1 h clamp, trigger cases migrated to trigPin; device bumped to 1.1.0; GUI checked (shared chip clickable, 23 trigger options, 5000 ms window accepted). - docs (both languages): CHANGELOG 0.11.0 + device version table, DEVICE-API passive metadata + instrument section, README capability row, ROADMAP probe-freedoms bullet, AGENT rule 3.11; version synced to 0.11.0.
140 lines
7.6 KiB
Markdown
140 lines
7.6 KiB
Markdown
**English** | [简体中文](ROADMAP.zh-cn.md)
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# Roadmap
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## Logic analyzer — shipped in peris 0.10.0, probe freedoms in 0.11.0
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- ✅ `logic-analyzer.js`: multi-channel GPIO waveform capture (up to 8
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pads, one trigger: channel + edge or Immediate, guest-time window,
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auto re-arm). Driven levels 1/0, released pads Z, times in guest µs.
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Rides the M4 scheduler (arm 1000 watch, fine lease per `resolution`
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preset: 20/100/300); 20 000-edge buffer freezes with an `overflow`
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flag. Shared logic in `peris/devices/la-lib.js`.
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- ✅ 0.11 probe freedoms: `static passive = true` — a probe listens only,
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claims no pad and may clamp onto ANY in-use GPIO (conflict check and
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wired-AND skip passive pads; other devices' pickers ignore them; the
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channel grid never disables a GPIO). Trigger became `trigPin` (any GPIO,
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independently subscribed, off-channel triggers fine); the window cap
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lifted to 1 h of guest time (the edge buffer is the natural limit).
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- ✅ Floating analyzer window: draggable, resizable, non-modal popup
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(fixed position, no backdrop — the page underneath keeps working);
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geometry persisted. One `drawWaveform` painter feeds the popup, the
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details mini-preview and the row icon; channels picked from a GPIO grid
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(occupied pins shown as shared, never disabled). Framework:
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`ctx.pinLevel`, `ViewHost.pinInfo`, `View.destroy` (row
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removal/rebuild teardown).
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- ✅ Saleae-style plot interactions: wheel zoom anchored at the cursor,
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drag pan, double-click/F fit; hover measurement shades the pulse and
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reads level · width · period · frequency · PWM duty; A/B cursors with
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Δt + 1/Δt; lane selection + ‹/›/←/→ edge jumping; lane gutter shows the
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right-edge level per channel.
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- Tests: readout math + capture state machine units, `sigbus.pinLevel`,
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smoke S13 (P4 soft-I2C bus capture). Ideas not in v1: pre-trigger
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buffer, incremental edge streaming during a run, protocol decoders on
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top of a capture (I2C/NEC annotations) — the frozen buffer already
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carries everything a decoder needs.
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## MAX7219 display — shipped in peris 0.9.0
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- ✅ `max7219.js`: the 8-digit LED driver on a firmware bit-banged
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DIN/CLK/LOAD bus (hardware SPI stays invisible — M0). Level-driven shift
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engine (MSB-first, words latched on the LOAD rising edge, misaligned
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frames dropped and counted, never garbled) + datasheet register model
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(Code B decode with independent DP, intensity PWM, scan limit,
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shutdown / display test, power-on defaults). 8×8 matrix and 7-segment
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Views auto-selected from the decode-mode register; daisy chains share
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the three pads. Shared logic in `peris/devices/max7219-lib.js`.
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- ✅ Real-firmware integration: smoke S12 boots the gun 0.1.0 release
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(ESP32-S3, delay-free bit-bang — edges ~20 instructions apart, the
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tightest pulses the M4 scheduler resolves: fine lease at the floor 20,
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arm 60) and decodes its `display_init()` with zero drops;
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`examples/esp32s3-gun.json` wires the display for the browser.
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## M4 · Bit-bang protocol devices + IR — shipped in peris 0.8.0
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- ✅ `bitbang-i2c-slave.js`: 24C02 EEPROM and BME280 models behind two
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firmware bit-banged GPIOs (SCL/SDA). Level-driven engine (open-drain
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model); the slave answers on the SDA input path, which the master sees
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while it releases the pad. Shared logic in `peris/devices/i2c-lib.js`
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(engine, register models, bit-exact Bosch compensation). Constraint
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documented: hardware I2C/SPI buses cannot be tapped (M0) and push-pull
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masters that never release SDA cannot be answered; clock stretching not
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modelled.
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- ✅ `ir-nec.js`: NEC codes captured from firmware **bit-bang** transmissions
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(fine-batch edge sampling → burst envelope) and from **RMT** channels
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(a 34-word frame fits the post-TX channel RAM; the emulator leaves
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`APB_MEM_WADDR` at 0, so mid-TX stitching is out — M4 probe). Decoder is
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fully ratio-based: the guest clock runs ~50% of nominal through
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`esp_rom_delay_us` (measured), so absolute-µs windows would misjudge.
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Shared logic in `peris/devices/nec-lib.js`.
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- ✅ High-rate sampling scheduler (`src/core/scheduler.ts`): per-device
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leases — a standing arm batch (~1000 instr) while the bus is idle, fine
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batches (~300 instr) while a transfer is in flight; leases expire on
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deadline or CPU-sleep fast-forward. Worker and tests share
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`runtime.batchSize()`.
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- ✅ Framework: `sharedBus` device metadata (I2C slaves legally share
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SCL/SDA) with wired-AND input arbitration; `cyclesPerUs` on the device
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ctx.
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- Test firmware P4 (soft-I2C master at ~20 kHz, forced BME280 measurements
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with C-side compensation cross-checked bit-exactly by the smoke test,
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NEC via both paths) + unit tests `tests/unit/protocol.test.mjs` +
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smoke S10/S11.
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## M3 · WS2812 addressable LEDs — shipped in peris 0.7.0
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- ✅ `ws2812.js`: polls the RMT channel RAM (M0 verified Q3b PASS),
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symbols → bitstream → GRB frames; reset-symbol resync + leading-zero
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alignment (the M3 probe refined the model: one RMT word per WS2812 bit,
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48-word wrap, a zero transmit terminator after the reset — details in
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FEASIBILITY.md). Shared logic in `peris/devices/ws2812-lib.js`.
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- ✅ Strip / ring / matrix Views; GRB/RGB order, brightness cap and gamma
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configurable; smooth frame interpolation like the M2 PWM bulbs
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(reusing the `ledc-lib.js` animator).
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- ✅ Known limitation, documented and surfaced in the UI: the 48-word
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channel RAM keeps only the **last 46 bits** of a frame, so strips longer
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than ~2 LEDs show only their tail (same as real C3 hardware); the View
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draws unrecoverable LEDs hollow. `CHnSTATUS` gates decoding while a
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transmission is in flight.
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- Performance: JS decoding measures far below any budget (one 192-byte
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read + a 48-word compare per batch); the wasm-helper escape hatch was
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not needed. Lifting the 46-bit limit would need the M4 fine-batch
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scheduler (sampling the RAM repeatedly *during* a transmission), not
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faster decoding.
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## M2 · PWM dimmed LED — shipped in peris 0.6.0
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- ✅ `pwm-led.js` + `rgb-led.js`: each LEDC channel's `DUTY_R` register is
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read every batch for the exact duty cycle, no aliasing (approach verified
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in M0: Q2b PASS).
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- ✅ Channel→pin mapping: `GPIO_FUNCn_OUT_SEL_CFG` (LEDC ch0–5 = 45–50)
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implements auto-discovered wiring that follows firmware rewiring; manual
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channel selection also allowed.
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- ✅ Breathing effect with smooth rendering: canvas brightness
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interpolation (one rAF animator per plugin repaints bulb + row icon).
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- Shared logic in `peris/devices/ledc-lib.js`; framework hooks
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`Device.onBatch()` + `ctx.mmio` (see DEVICE-API.md).
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## M5 · Upstream capability tracking (not under our control)
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These need APIs the wasm does not expose today; progress depends on new
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esp-emulator releases (upgrade procedure in UPGRADE.md):
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| capability | required upstream interface | status |
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|---|---|---|
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| hardware I2C device models | i2c slave/device bridge API (CLI-only `--i2c-dev`, dumb registers only) | ❌ |
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| hardware SPI peripherals (SD card etc.) | spi device bridge | ❌ |
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| SPI/RGB565 displays | spi/lcd_cam (the peripheral itself is not emulated) | ❌ |
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| real touch peripheral | touch peripheral emulation | ❌ (touch button stands in with GPIO semantics) |
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| ADC (potentiometers etc.) | adc emulation | ❌ |
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| I2S audio | i2s emulation | ❌ |
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| UART1 peripheral | wasm-exposed uart1 (CLI has `--uart1-tcp`) | ❌ |
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| state snapshot save/restore | save/load API | ❌ |
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## Maintenance items
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- ~~`update_esp_emu_browser.bat`~~ — solved differently: `tools/fetch_esp_emu.py`
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downloads/unpacks any esp-emulator release (`--version <ver>`), see
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UPGRADE.md.
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- `src/core/mmio/`: add the C5/C6/H2/P4/S3 address tables (extracted from each
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chip's IDF soc headers, same method as M0).
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